Spartan 3 FPGA IO Standard Config

Thread Starter

kar_p

Joined Dec 19, 2011
7
Hello,

I am using spartan3 FPGA board to detect data as logic 1 for voltage level greater than 3V and logic 0 otherwise.

I am stuck on setting the IO standard for output of FPGA. I did write a ucf file and was just sending random signal varying from 0v to 4v to the Input pin and the Spartan 3 FPGA is detecting any signal greater than 2.3V as logic 1.

Could anyone suggest me how to change the IO standard of Spartan 3 FPGA to 3V.

Any suggestion would be greatly appreciated.
Thanks in advance!!
 

kubeek

Joined Sep 20, 2005
5,794
Could anyone suggest me how to change the IO standard of Spartan 3 FPGA to 3V.
3V logic is NOT the same thing as "anything greater than 3V is 1"
3V logic would have the logic 1 threshold around the 2.3V, while 5V TTL logic would be closer to what I think you want.

Are you sure you need to interface a 5V logic? Wouldn´t a comparator be a better choice?
Also, what voltage range should be logic 0?
Usualy it is defined in the fashion of 0-0.7V is a logic 0 and >2.3V is a logic 1, anything between is undefined.
 

Thread Starter

kar_p

Joined Dec 19, 2011
7
Thank You for your reply. I really appreciate it.

Yep, I actually need to interface FPGA to a 5v logic. Logic 0 should be in the range 0-1.2v and logic1 should be >3v.

The reason I am using a FPGA instead of comparator is, I will be getting continuous data and I need to store the data and work on it.
 

kubeek

Joined Sep 20, 2005
5,794
If it is pure digital data, a simple resistor divider should work nicely on inputs. On outputs I would use open collector and a pullup to the right voltage.
 

Thread Starter

kar_p

Joined Dec 19, 2011
7
It is not a pure digital data......the data that I am collecting into FPGA is full wave rectified data......so I think I need to change the IO standards of FPGA.....but I'm not sure how to change it
 

kubeek

Joined Sep 20, 2005
5,794
It is not a pure digital data......the data that I am collecting into FPGA is full wave rectified data......so I think I need to change the IO standards of FPGA.....but I'm not sure how to change it
So you´re feeding the data into an ADC?
 

Thread Starter

kar_p

Joined Dec 19, 2011
7
It's not an ADC. I'm directly feeding the full wave rectified data into FPGA Input pin. For testing purpose, I connected the FPGA output pin to LED. The LED is blinking whenever the full wave rectified signal is greater than 2.3v. But, I would like to change it to 3 or 3.3v.

Someone mentioned that we can change the i/o standards to the level we would like by making some changes in the user constraint file of FPGA. I am not able to figure out how to make those changes.
 

kubeek

Joined Sep 20, 2005
5,794
It's not an ADC. I'm directly feeding the full wave rectified data into FPGA Input pin. For testing purpose, I connected the FPGA output pin to LED. The LED is blinking whenever the full wave rectified signal is greater than 2.3v. But, I would like to change it to 3 or 3.3v.

Someone mentioned that we can change the i/o standards to the level we would like by making some changes in the user constraint file of FPGA. I am not able to figure out how to make those changes.
I think you should use a comparator and a trimpot to set the threshold. Relying on a logic level of the FPGA is not a good practice.
 

Thread Starter

kar_p

Joined Dec 19, 2011
7
I will think of using a comparator. But I am not sure what a trimpot is. I never used that. I will go through it. Thanks for your help and suggestions. I really appreciate it :).
 
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