Greetings, I am having a difficult time finding verification if I am interpreting a schematic correctly. Specifically, it is a schematic by N1AL (Alan Bloom) for "A Modern Grid Dip Oscillator" in the May 2003 edition of QST. http://www.qsl.net/k8mcr/downloads/Modern_GDO.pdf

Q1,Q2 & Q3 are MPF102 N-Channel JFETs. I am using the SMD version, MMBF102 as I have more to spare than the TO-92 MPF102's.

My confusion is is the connection of Q1 & Q2 -

"A pair of source-
coupled N-channel JFETs (Q1 and Q2) form the oscillator
portion of the circuit."

Q2 is a mirrored version of the schematic symbol for an N-Chan JFET (Q1). I recognize the layout of the JFET with the gate on the left side, the drain on bottom and the source on top. However, in my mind when it is mirrored and the gate is now on the right side of the schematic symbol, it's drain and source remain oriented the same as the other symbol (drain on bottom, source on top).

I cannot seem to find a good representative image to help me decipher a source coupled pair like this. If my current interpretation of the schematic is correct, the drains of the two JFETs in this oscillator are coupled.

If I have not made my question too confusing, can someone please take a moment to help clarify my confusion. Would he MPF102's in the form of a source coupled pair forming an oscillator have the drains connected, or am I misunderstanding the mirrored JFET symbol (with gate on right side, does D & S switch locations)?

Thank you so much for your time and if i need to upload a clip of the schematic and am capable of doing so with my low post count, I certainly will.

Thanks again for your time.
-evile

 

I don't think you are reading the schematic correctly. For both Q1 and Q2 the drain is toward the top of the diagram, and they are mirror images about the vertical axis. The source nodes are connected together as it says in the text. Since Q1's gate is connected to the negative supply (-3 volts), I'm thinking it is biased into it's linear range. Drains being connected to the more positive voltage level (GND in this case) is not an uncommon thing.

 

You are absolutely correct. I believe my confusion arose after looking at the datasheet provided to be a reference for the pinout of my MMBF102's (by the supplier). It is a datasheet for the SMD version of J310's: http://www.onsemi.com/pub_link/Collateral/MMBFJ309LT1-D.PDF

This schematic symbol, for an N-Channel JFET shows the drain on bottom and source on top. Is there something I am not understanding about the use of the JFET schematic symbol & its orientation? Perhaps the schematic represented in the datasheet is that way for a specific reason?

Thank you so very much for your assistance. It is greatly appreciated.

 

In hopes to clarify any confusion and reduce the amount of PDFs needed to be opened to assist me...

s th

Heres a clip from the OnSemi's MMBFJ310 datasheet. I am using MMBF102's and my supplier states that these two SMD RF JFets have the same pinout. But is there a difference between the schematic symbols that should be used? They are both N-Channel JFETs.


Here is the schematic in question.

Following the schematic symbol from the datasheet, it appears to me the drains are connected, not the source (although I understand the opposite to be true, I am hoping to understand why that is).

I'm certain I am missing something obvious, as I tend to do. Hopefully, the images will make it easier to understand my incorrect perspective.


edit: Just a thought, is it because the positive & ground supply lines are reversed (see original post for PDF w/ full schematic or google: modern GDO alan bloom)


Thank you.

 

I think the symbol for a JFET is ambiguous with respect to which terminal is the source and which terminal is the drain. IIRC this ambiguity might have been on purpose. Unlike a BJT I think I remember reading about a JFET not caring about polarity.

Checkout the JFET symbols in the wiki that remove the ambiguity.
http://en.wikipedia.org/wiki/Transistor

and this quote
The JFET gate is sometimes drawn in the middle of the channel (instead of at the drain or source electrode as in these examples). This symmetry suggests that "drain" and "source" are interchangeable, so the symbol should be used only for those JFETs where they are indeed interchangeable.

Officially, the style of the symbol should show the component inside a circle (representing the envelope of a discrete device). This is true in both the US and Europe. The symbol is usually drawn without the circle when drawing schematics of integrated circuits. More recently, the symbol is often drawn without its circle even for discrete devices.

In every case the arrow head shows the polarity of the P-N junction formed between the channel and gate. As with an ordinary diode, the arrow points from P to N, the direction of conventional current when forward-biased. An English mnemonic is that the arrow of an N-channel device "points in".

 

Wow, thank you so much for your assistance.

I may be confused about the statement: This symmetry suggests that "drain" and "source" are interchangeable, so the symbol should be used only for those JFETs where they are indeed interchangeable.

by the way in which it is worded, it seems to suggest that their is no physical difference between the actual drain and source of the JFET. As though it is the way in which it is applied in a circuit which designates that leg of the device as either the drain or the source. This doesn't seem correct to me though, so I am going to have to do more reading up on them before I continue on with the project.

Thank you kindly for your generous support!

 

Wow, thank you so much for your assistance.

I may be confused about the statement: This symmetry suggests that "drain" and "source" are interchangeable, so the symbol should be used only for those JFETs where they are indeed interchangeable.

by the way in which it is worded, it seems to suggest that their is no physical difference between the actual drain and source of the JFET. As though it is the way in which it is applied in a circuit which designates that leg of the device as either the drain or the source. This doesn't seem correct to me though, so I am going to have to do more reading up on them before I continue on with the project.

Thank you kindly for your generous support!

When the JFET was first fabricated I think this was exactly the case. The device was symmetrical and could be used in either orientation. In the roughly half century since those first JFET transistors were fabricated, the methods and geometries have changed to the point where it may no longer be the case that they are symmetrical.

 

Thank you, again, papabravo. I'm not sure if I should make a new post, since this is a separate question. But I am eager to build this GDO & still a bit confused about something.

Alan states in the article:

Note that the battery is connected with the positive terminal to ground, backwards from the normal arrangement.
​

Looking at the image in the article of the internal view of the build, it does appear that he simply placed the batteries into the 2xAA holder backwards. But as I look at the schematic and see all the ground connections, I just am not 100% positive that all of them really are meant to goto the positive rail (which would be the ground rail, if the batteries were not backwards).

Does this schematic indicate that I am really to make all of these ground connections, which will actually goto the +3VDC via the backwards batteries? In that case, should I not ground the circuit to the metal chassis for shielding?

I hope that its okay I asked this within the same thread rather than post a new topic. If I should make a new topic, please inform me. Thank you.

I posted the schematic below for reference.

​

 

Not every circuit operates between GND and some positive voltage. Especially in RF circuits operating between GND and some negative voltage is equally valid. I trust the statement in the text since it is consistent with the schematic. That is the more positive voltage is connected to the chassis.

I'm not having much luck viewing your images. Can you see them in your browser?

 

Thanks PapaB. I'm familiar with negative & split supply circuits, but not used in RF. This particular GDO circuit has been a bit challenging but educational for me.

I uploaded the images to postimage.org so I could paste in the forum here. I've never used it before though.

Heres a link to the schematic: http://postimg.org/image/cw5q1kbdl/



Does that work for you?

By the way, I ended up using one of my two J309's for the third, unpaired, JFET (Q3), instead of the MMBF102 Surface mounts and my last two MPF102's for the pair (Q1 & Q2). I was hoping to use the MMBF102's since I have 10 of them but decided to go with the TO-92's for easier corrections to any mistakes I may make during the process. I'm saving up my pennies to hopefully get some more MPF102's in the future.

Thanks again for all of your assistance, I've learned much already. Best wishes.

 

for reference, heres the other images from my earlier posts.. hopefully this works.

 

Surprising all the images are now there. It's like they were not available when the page was first rendered, but have subsequently finished downloading and are all available now. It might have helped that I ran CCleaner earlier this afternoon and dropped 1.6GB of cruft.