Sony CCD chip - how do the clocks work

Discussion in 'General Electronics Chat' started by davebee, Oct 22, 2008.

  1. davebee

    Thread Starter Well-Known Member

    Oct 22, 2008
    My brother-in-law dropped his girlfriend's video camera onto some rocks and totally smashed it, so I took it apart and am trying to understand the CCD, a Sony ICX226AK, which wasn't damaged at all.

    Sony provides a datasheet describing the vertical and horizontal clocking requirements in a way that if you already understand the chip, you could probably make sense of them, but I can't figure out a few things - can anyone help?

    Overall, there are 4 vertical clock lines and two horizontal clock lines. The vertical clocks shift charges into a horizontal shift register, then the horizontal clocks shift the linear register out to the output pin for ADC conversion.

    There are four vertical lines because of the way it detects color, with what they call complementary color mosaic filters; it's a little complicated and I don't completely understand it but doesn't look too hard to eventually figure out.

    The ccd is an interline transfer design. The data sheet shows that two of the four vertical clock lines seem to have three states; V1 and V3 both have an additional high-going pulse that I guess does the interline image transfer, but nothing in the data sheet describes this at all. Can anyone expand on that?

    There are two horizontal clock lines and a reset clock line, but no description of how they must be used. There is a single diagram showing that it appears that the two horizontal lines are clocked exactly in opposite phase, and I guess that after every transition, you measure the output then pulse the reset pin to clear the charge. Does this sound right?

    Thanks for any help,
  2. scubasteve_911

    AAC Fanatic!

    Dec 27, 2007

    I gandered through the datasheet, and I must say that it was one of the most complex and confusing datasheets I have ever read. You're not alone in your confusion.

    Did you see the vertical transfer clock equivalent circuit? Crazy stuff. Sorry I cannot help, I just wanted you to know that I also thought it was a little unclear...

  3. davebee

    Thread Starter Well-Known Member

    Oct 22, 2008
    Thanks for the second pair of eyes, Steve. I thought I needed new glasses when I first saw those three separate levels in the vertical pulse logic.

    I found a clue. The CCD datasheet shows a driver chip CXD1267AN, and the drivers data sheet also shows that the two vertical lines V1 and V3 have three-voltage logic. It shows how the inputs to drive V1 and V3 both have two normal logic inputs so that a microcontroller can select either normal vertical register clocking or the extra high voltage to do the image transfer. It even recommends the voltage of 12V for the V1 and V3 high level, where normal clocking only needs 3V.

    So maybe that'll be enough to make some progress!