# Solution to metastability in VHDL

#### eronenveeti174

Joined Sep 16, 2020
1
https://en.wikipedia.org/wiki/Metastability_(electronics)

In short: Metastability is a situation where flip-flop gets stuck between 1 and 0 on certain inputs for an indefinite amount of time.

I've solved this problem by placing a "deoscillator" to the circuit, which stops it from looping between 1 and 0.

My solution can be found from here:
https://gitlab.com/eronenveeti174/deoscillated-flip-flop-in-vhdl/

I wanted to share this in case someone else is also interested in controlling metastability. If someone has any hint on how to publish this solution more widely then all the help is welcome.

#### Deleted member 115935

Joined Dec 31, 1969
0
Welcome to the world of asynchronous to synchronous conversion.

meta stability is a statistical entity,

Meta stability happens when the input is is the "unknown" region at the point the clock edge is active.

The answer to metastability , is as its a statistical thing, impossible to actualy make 100 % certain.

The answer is, to register the input signal into a shift register

assume you have inp_sig as a std_logic_vector of say 2 downto 0, an asyncronous input of inp_asy,

inp_sig<= inp_sig( inp_sig'left -1 downto 0 ) & inp_asy;

the meta stable proof output you want is

inp_sig( inp_sig'left);

Having said all that

your circuit, has two inputs, and its not a meta stable circuit, but a switch de bouncer.
which in itself needs to be driven by a meta stable proof input,

or use this code

https://www.digikey.com/eewiki/pages/viewpage.action?pageId=4980758

#### soyez

Joined Aug 17, 2020
51
https://en.wikipedia.org/wiki/Metastability_(electronics)

In short: Metastability is a situation where flip-flop gets stuck between 1 and 0 on certain inputs for an indefinite amount of time.

I've solved this problem by placing a "deoscillator" to the circuit, which stops it from looping between 1 and 0.

My solution can be found from here:
https://gitlab.com/eronenveeti174/deoscillated-flip-flop-in-vhdl/

I wanted to share this in case someone else is also interested in controlling metastability. If someone has any hint on how to publish this solution more widely then all the help is welcome.
The most well-known approach to endure metastability is to include at least one progressive synchronizing flip-failures to the synchronizer. This methodology considers a whole clock period (aside from the arrangement time flip-flop) for metastable occasions in the main synchronizing flip-failure to determine themselves.