Solar NiMH charger - Schematic and PCB review!

Discussion in 'The Projects Forum' started by emoney, Aug 20, 2010.

  1. emoney

    Thread Starter New Member

    Aug 20, 2010
    Project goal: safely charge and discharge three NiMH cells (1.2 V, 2300 mAh nominal) in series.

    Approach: use two comparators to isolate batteries from the load and from the charging source when overvoltage and undervoltage conditions are reached.

    Request: Please look at my schematic, simulation traces in LTSpice IV, and PCB design and tell me if there's anything wrong (let me know if you need more info about the names of traces on the simulation). I'm almost ready to submit this for manufacture. I'm most worried about the trace width and clearances on the PCB (assuming the schematic works). As for I/O to the board, I'm thinking of using mechanical connectors such as those screw-in metal things to secure the threaded wire (to be placed where the X'ed holes are).

    Attachments: 1) schematic, 2) board 3) simulation in LTSpice IV 4) traces from simulation 5) close-up of hysteresis in low-voltage cutoff from simulation 6) datasheet for p-channel FET.

    Operation: Battery cell voltage approximated with voltage divider through R1 and R2, which divides the battery pack voltage by three. This voltage is input to two comparators in dual package, LM393. The other input is a 1.0 V reference voltage produced by a shunt precision reference, ADR510. The high-voltage cutoff is on the left. It compares the reference and the cell voltage multiplied by about 2/3 through R4 and R5 since the high-voltage cutoff is about 1.45 V and 1/1.45 = 20/29 ≈ 2/3. When the cell voltage through this voltage divider rises above 1.0 V, the comparator's output is pulled to the battery pack voltage through pull-up resistor R6, which turns off the p-channel FET, isolating the batteries from charging.

    Likewise, the low-voltage cutoff on the left compares the cell voltage to the reference of 1.0 V, because the low-voltage cutoff is 1.0 V. When the cell voltage drops below 1.0 V, the output of the comparator is pulled to the battery pack voltage through pull-up resistor R7, isolating the battery pack from the discharging load. There is hysteresis on the output of the low-voltage comparator to prevent flickering of the LED load.
  2. SgtWookie


    Jul 17, 2007
    It would help a great deal if you would include the LTSpice .asc file. It does not have to be .zipped before uploading.

    It is not a good idea to charge batteries in series. Even when new, there will be slight variations between battery capacity. As they age, the variations will become more pronounced. This can actually lead to a weaker battery being forced into a reversed polarity, which will likely destroy it.

    In Cadsoft Eagle, it is very helpful to turn off the PINS layer in the schematic before you export a .png image; otherwise the schematic gets rather cluttered looking.

    It appears that you are using symbols from Supply1.lbr or Supply2.lbr. While this will cause the board to route air wires between those points, you will not have a pad to connect wires to, or a place to install a connector.

    Try using wirepad.lbr, and connect some wire pads to your wires. Use the NAME function to indicate their function; eg "GND", "+5V", etc. The VALUE field for wirepads doesn't seem to show up in the board. Also, if space is tight, you can make the board less cluttered by turning off tnames/bnames than by turning off tvalues/bvalues.

    For schematics, the basic guidelines are inputs come from the left, outputs go towards the right - more positive voltages near the top, more negative towards the bottom.

    I much prefer to show MOSFETs with their gates at the left (since it's an input) and for N-ch MOSFETs, the source terminal down; P-ch MOSFETs get the source terminal on top. However, for your type of circuit, it's common for P-ch MOSFETs to be shown with the source terminal to the left, drain to the right, and gate down. It simply makes comprehending the schematic that much easier.
    Last edited: Aug 20, 2010
  3. emoney

    Thread Starter New Member

    Aug 20, 2010
    Hi Wookie,

    Thanks for your help. I'll be sure to keep those conventions in mind for my next project. I've attached the .asc file I used to generate the simulations as well as an updated .sch and .brd file that's cleaner.

    I also know that there are many things in the overall design of this system that could be improved. I'm just concerned about whether or not it will work on the basic level that I described above.

  4. retched

    AAC Fanatic!

    Dec 5, 2009
    Could you supply the battery_nimh and the XOPAMP files as well?
  5. emoney

    Thread Starter New Member

    Aug 20, 2010
    Oh, sorry. Of course -- they are attached.
    retched likes this.
  6. emoney

    Thread Starter New Member

    Aug 20, 2010
    Again, all -- just wondering if there is anything functionally wrong with my schematic and/or PCB design. This includes PCB trace clearances, overlaps, etc ... any feedback would be much, much appreciated.

    Thank you!