# slef biasing jfets

#### rodn.m

Joined May 3, 2006
12

briefly explain why the drain voltage is specified as being 5volts? (or VDD/2)

it refers to a jfet transistor amplifier circuit of a constant current source. it has a resistor in both the drain and source paths of the circuit, as well as the gate.

the supply voltage (VDD) is 10 volts +ve.

the question also refers to a transfer curve and a GATE/Source Voltage = 0.

My answer is (and i am hoping you can either add or comment on):

A JFET transistor amp needs to be biased using resistors that: give a drain voltage equal to half the supply voltage.

A gate source reverse bias voltage to give a drain current of IDSS/2.This is the most linear part of the transfer curve, which is the operating point of the circuit, if distortion is to be avioded.

Question 2.
as on the attachment for the same circuit. They ask if Rs was reduced, describe the effect this would have on Vd and Vs of the circuit.

My answer: By the equation: Vs=Id*Rs

Id=.005v
Rs=500ohms Vs=.005*500=2.5v
If Rs=250ohms Vs=.005*250=1.25v
therefore Vd=Id*Rd

If Rd=1k Vd=.005*1000=5 v
Vd would remain unchanged if Rs reduced

If this is not correct, could u help please?

the circuit i refer to is on the right hand side of the page attached.

#### n9352527

Joined Oct 14, 2005
1,198
For question 1, I would say that the reason Vd is set to 0.5VDD is to obtain the largest voltage swing possible. This is necessary, as you've mentioned, to avoid distortion due to clipping.

For question 2, Have you considered that by changing Rs, the biasing voltage (Vgs) would change as well? If the biasing is different, then it would follow that the Idss would also be different and of course both Vd and Vs would be different as well.

#### hgmjr

Joined Jan 28, 2005
9,029
Originally posted by rodn.m@May 4 2006, 10:48 AM

briefly explain why the drain voltage is specified as being 5volts? (or VDD/2)

it refers to a jfet transistor amplifier circuit of a constant current source. it has a resistor in both the drain and source paths of the circuit, as well as the gate.

the supply voltage (VDD) is 10 volts +ve.

the question also refers to a transfer curve and a GATE/Source Voltage = 0.

My answer is (and i am hoping you can either add or comment on):

A JFET transistor amp needs to be biased using resistors that: give a drain voltage equal to half the supply voltage.

A gate source reverse bias voltage to give a drain current of IDSS/2.This is the most linear part of the transfer curve, which is the operating point of the circuit, if distortion is to be avioded.

Question 2.
as on the attachment for the same circuit. They ask if Rs was reduced, describe the effect this would have on Vd and Vs of the circuit.

My answer: By the equation: Vs=Id*Rs

Id=.005v
Rs=500ohms Vs=.005*500=2.5v
If Rs=250ohms Vs=.005*250=1.25v
therefore Vd=Id*Rd

If Rd=1k Vd=.005*1000=5 v
Vd would remain unchanged if Rs reduced

If this is not correct, could u help please?

the circuit i refer to is on the right hand side of the page attached.
[post=16801]Quoted post[/post]​
Greetings rodn.m,

Looks like you have arrived at fairly reasonable answers.

It is refreshing to see a topic poster in the "homework help" forum post their initial efforts at solving the problem and ask for confirmation of their results. A number of posters to "homework help" just post the question and ask for one of the members to provide the answer.

hgmjr

#### rodn.m

Joined May 3, 2006
12
Originally posted by n9352527@May 5 2006, 04:08 AM
For question 1, I would say that the reason Vd is set to 0.5VDD is to obtain the largest voltage swing possible. This is necessary, as you've mentioned, to avoid distortion due to clipping.

For question 2, Have you considered that by changing Rs, the biasing voltage (Vgs) would change as well? If the biasing is different, then it would follow that the Idss would also be different and of course both Vd and Vs would be different as well.
[post=16805]Quoted post[/post]​