simulation error

Thread Starter

saj

Joined Oct 25, 2013
3
View attachment 800um-104.asc

View attachment exacttext.txt
hi,
I tried using my own model file for NMOS4 & PMOS4 and I get the following error


Error on line 831 : .model n1 nmos vto=0.7 kp=110u gamma=0.4 phi=0.7 lambda=0.04 cgso=220p cgdo=220p cgbo=700p cj=770u mj=0.5 cjsw=380p mjsw=0.38 tox=14n nsub=3e16 nfs=7e+11 xj=0.2u ld=0.016u +uo=660 delta=2.4 theta=0.1 eta=0.1 kappa=0.15
* Unrecognized parameter "nfs" -- ignored
* Unrecognized parameter "xj" -- ignored
* Unrecognized parameter "delta" -- ignored
* Unrecognized parameter "theta" -- ignored
* Unrecognized parameter "eta" -- ignored
* Unrecognized parameter "kappa" -- ignored
Model "n1": Oxide thickness thinner than recommended for a level 1 MOSFET.
Instance "m§nmos": Length shorter than recommended for a level 1 MOSFET.
Instance "m§nmos": Width narrower than recommended for a level 1 MOSFET.
.OP point found by inspection.
.step v1=0
.step v1=1
.step v1=2
.step v1=3
.step v1=4
.step v1=5

Date: Tue Mar 25 21:30:08 2014
Total elapsed time: 0.094 seconds.

tnom = 27
temp = 27
method = trap
totiter = 89
traniter = 0
tranpoints = 0
accept = 0
rejected = 0
matrix size = 4
fillins = 0
solver = Normal
Matrix Compiler1: 7 opcodes
Matrix Compiler2: 20 opcodes
 

Papabravo

Joined Feb 24, 2006
21,159
It might be helpful to know which simulator we're talking about. Also, most of us here are hobbyist types who put chips on boards, not chip designers. The vast majority would not be able to help. Still there is a off chance that a former chip designer is lurking here, so it can't hurt to ask and it might help.

I've done lots of hours of simulation at the behavioral/gate level but the device level is beyond my scope.
 

Papabravo

Joined Feb 24, 2006
21,159
My advice to you is to post your question to the LTSpice Yahoo group. The guy who wrote LTSpice hangs out there as well as some folks who know how to make it sing songs and do dances.
 
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