could some1 please help me? i would like to know if: ABC’D’ + AB’C’D + ABCD + ABCD’ can be simplified to :AB
You can probably benefit from reading the boolean algebra tutorial section in the All About Circuits website. After you have review the material give your problem a go and then post your efforts. Someone will be sure to help you make any corrections that are needed. hgmjr
could some1 please help me? i would like to know if: ABC’D’ + AB’C’D + ABCD + ABCD’ can be simplified to AB what i did was: ABC’D’ + AB’C’D (B+B') = 1 = AC' (B+B' + D+D') (D+D') =1 so this = AC'D' then ABCD + ABCD’ = ABC (D+D') (D+D') =1 so this = ABC then AC' + ABC = AB (C'+C) (C+C')= 1 so this = AB is what i have done here correct? =
Why the D' (bolded)? It doesn't follow on further down your calculation. Where does the B come from in the first expression: AC' (bolded)? Other than this it seems pretty good. Dave
oh ok i get what ur sayin' it shouldn't be there. so the answer is correct? the next part is "AB'C'D" added to the answer from the first part AB + AB'C'D = A (B + B' +C' + D) = AC'D' is this correct? i just want to make sure so that i get the next question right which is to Design and demonstrate a NAND gate implementation of the circuit for the simplified expression
The first bit simplifies to AC' - which you have correct (provable by De Morgans theorum). ABCD + ABCD' = ABC So you have AC' + ABC Can I ask which theorum you have used to simplify this to AB? Dave
So you have AC' + ABC can't you do (C' + C) = 1 so u would then be left with A + AB ? which could be simplified to AB ? im kinda lost now
You can't make that assumption because B is not a common factor in the first expresion. A + AB would simplify to A, not AB. Ref: http://www.allaboutcircuits.com/vol_4/chpt_7/5.html at the top Ok, here is how I got to A(B + C'): AC' + ABC We know (B + B') = 1, so: AC'(B + B') + ABC Multiple out: ABC' + AB'C' + ABC Take out AB as a common factor in the first and third expressions: AB(C + C') + AB'C' And we know (C + C') = 1, so: AB + AB'C' Take out A as a common factor: A(B + B'C') And (B + B'C') simplifies to B + C' Ref: http://www.allaboutcircuits.com/vol_4/chpt_7/5.html half way down. Therefore you get: A(B + C') Happy with that? Dave
yes thank you the next part is "AB'C'D" added to the answer from the first part, which would give: A(B + C') + AB'C'D so then: AB + AC' + AB'C'D you can take out A as a common factor A (B + C' + B'C'D) which rule would u appl to this part? would it be C'C' = C' so u get A (B + B'C'D)
Can I ask, do you have an expression you are aiming to simplify A(B + C') + AB'C'D to? Or are you just trying to get it in a minimal form (i.e. least number of terms)? Dave
i am trying to simplify it so that i can Design a NAND gate implementation of the circuit for the simplified expression. to do this would i need to get it in minimal form?
Ok, if thats the case you need to look at De Morgans theorums (ref: http://www.allaboutcircuits.com/vol_4/chpt_7/8.html) This is quite confusing so bare with it: A(B + C') + AB'C'D Take out A as a common factor: A(B + C' + B'C'D) Double not the function (I have used a double ' (i.e. '') for this, note this doesn't change the function. Can you see why [NOT(NOT(C)) = C]): (A(B + C' + B'C'D))'' Use the De Morgan's identity (AB)' = A' + B' So you get: (A' + (B + C' + B'C'D)')' For the expresion (B + C' + B'C'D)' using the De Morgan's identity (A + B)' = A'B': (B + C' + B'C'D)' = (B'C''(B'C'D)') C'' = C So this simplifies to: (B'C(B'C'D)') So the whole expression is: (A' + (B'C(B'C'D)'))' Using the De Morgan's identity (A + B)' = A'B': A(B'C(B'C'D)')' Finally, double NOT the function: (A(B'C(B'C'D)')')'' This expression, although it does not look like it, can be implemented purely using NAND gates. Note: If you tie the two inputs of a NAND gate together you get a NOT gate. Apologies that this is very confusing, I suggest that you write down what I have done above in your own terminology and aquaint yourself with the use of De Morgan's theorum (link above), pay very close attention to the brackets and the NOT expressions in the above. Post back any problems you have with the derivation and I will explain my ramblings better. If you want help with the implementation, then we can deal with that later. At the moment, you need to understand the derivation. Dave
could you please explain the double not fuction as we have not covered it in any of the lectures yet so i am not familiar with it and also would there be any other of doing it with out using the double not function?
A Double NOT Function is merely two NOT gates placed in series with each other such that they cancel the effect of each other. See the first explanation in this section, titled Double Inversion, the diagram should make it clear. Clearer? The Double NOT Function is a valuable (read as essential) tool in using De Morgan's theorums properly. A point to note about my above calculations is when I say A(BC)' this should be read as A AND NOT(B AND C). This what I mean about paying attention to the brackets and NOT expressions. Dave
ok so the answer... is it in its simplest form or is there anything else that could be done (A(B'C(B'C'D)')')''
The expression there can be simplified further for use in a NAND implementation. (A(B'C(B'C'D)')')'' Use the De Morgan's identity (AB)' = A' + B' So you get: (A(B'C(B'' + C'' + D'))')'' B'' = B and C'' = C So: (A(B'C(B + C + D'))')'' Multiply out (B'C(B + C + D')) (B'C(B + C + D')) = (B'BC + B'CC + B'CD') B'B = 0 and CC = C So: (B'C(B + C + D')) = (B'C + B'CD') And the full expression becomes: (A(B'C + B'CD')')'' Using the De Morgan's identity (A + B)' = A'B': (A(B'C)'(B'CD')')'' This is what I get in its simplest form, although I advise you check all of my calculations I verify none of these are correct - I have done that many of these today that there is a good chance I have overlooked something. If so, post it up and I'll check, if may just be a typo. As is always the case with these types of questions there are more than one answer and I am open to see how others may tackle this problem. The issue you now have is configuring the NAND gates to use the least number of gates possible. Dave