I'm having some confusion in my attempt to fill out the following truth tables. (See figure attached)

For now I've been focusing on trying to get the NAND FF figured out.

I look at the table and the initial value I'm given for my NAND FF is as follows,

S = 1, R = 1.

Now from what I've read about the NAND FF,

"It can be seen that when both inputs S = "1" and R = "1" the outputs Q and NOT(Q) can be at either logic level "1" or "0", depending upon the state of inputs S or R BEFORE this input condition existed."

But I don't have any state of inputs for S or R BEFORE this input condition, this is my initial input condition.

How do I deal with this?

 

It doesn't really matter which value you will fill in the first row of your table, as the second row is the "reset" row. No matter what you fill in the first row, the second row will be 0-1.

 

It doesn't really matter which value you will fill in the first row of your table, as the second row is the "reset" row. No matter what you fill in the first row, the second row will be 0-1.

So I can choose any value I want for the first row of my table?

I'm still a little confused about how I go about filling out my table, but I've made an attempt. How do things look so far?

EDIT: How does that look? I'm still not sure what values for Q and Q' I should insert for the Invalid State.

 

For my there is a error becaues in the table.
For NOR RS flip flop when S = 1; R = 1 then Q = 0 and /Q = 0 so we have invalid state (in the logical sense).
and for S = 0 and R = 0 we can not determine the output if we don't know the past.

And for NAND we have invalid state for S = 0 , R = 0, but for S=1 ; R=1 we have the same situation as for NOR RS for 0 0 on input.

 

Why you don't analysis the truth table for NOR; NAND gates.

 

For my there is a error becaues for NOR RS flip fop and
S = 1; R = 1 then Q = 0 and /Q = 1 so we have invalid state (in the logical sense).
and for S = 0 and R = 0 we can not determine the output if we don know the past.

And for NAND we have invalid state for S = 0 , R = 0, but for S=1 ; R=1 we have the same situation as for NOR RS

Okay so are you saying the first row in both my tables is incorrect? Or are you trying to tell me what the values of Q and Q' should be when there is an invalid state?

 

@Jony130

Can you rephrase post #4 please? I don't think I understand what you say.

@jegues

I would write "Keep State" in the rows of the NOR FF where S=R=0. The action of the FF is a function of the inputs not Q and Q'. Also maybe you would be more correct if you wrote X's or ? in the first row. But I don't know for sure what are the intensions of your professor.

 

Okay so are you saying the first row in both my tables is incorrect?

I'm trying to say that as for nor and nand gate the first row is not invalid state, it's stead state.

 

Okay but what about the last row, they are invalid state's for both the NOR FF and NAND FF.

If it's invalid how am I suppose to come up with values for Q and Q'?

 

Well very simple if you look at truth table for NOR gate
http://en.wikipedia.org/wiki/Logical_NOR#Truth_table
And now if we look at NOR FF diagram
http://upload.wikimedia.org/wikipedia/commons/5/53/RS_Flip-flop_(NOR).svg
It's clear know that for S = 1 then /Q = 0 and for R = 1 ---> Q = 0
So we have both outputs to a logic 0.

 

Okay, now I've got to fill out a truth table for the a Gated SR Latch.(see figure attached)

For the first two columns, "Before applying clock", all the values for Q and Q' should be the same, correct? Because when the clock is 0, the Gated SR Latch should keep its state.

For the second two columns, "After applying clock", this should be identical to a regular SR NOR FF, correct?

Is what I stated above correct?

 

When the clock is LOW, you get S=R=0, the "no change" state.
When the clock is HIGH, you get the actual values of S and R transfered to the NOR gates.

So, yes, you treat it in the same way.

 

When the clock is LOW, you get S=R=0, the "no change" state.
When the clock is HIGH, you get the actual values of S and R transfered to the NOR gates.

So, yes, you treat it in the same way.

Okay so the first two columns, "Before applying clock", should consist entirely of 0's?

EDIT: Wait, then the values for the first two columns (Q, Q') will be identical to S&R right?

So from top to bottom,

0,0
0,1
0,0
1,0
0,0
1,0
0,0
0,1
1,1

Right?

 

It's the same dillema as before. No matter what you fill them with, won't affect the next rows.

 

It's the same dillema as before. No matter what you fill them with, won't affect the next rows.

Yes, I agree that they can be anything, but is there any specific values I should be filling with?

 

If I were you I would fill with X's, like don't care. But if the professor has directed you elsewhere in the classroom, by all means follow his instructions.