# Simple question on characteristic equation.

#### MichealY

Joined Apr 9, 2009
49
Hi, the book Digital Design,Principles and Practices 3e by John F. Wakerly frustrated me on the characteristic equation of S-R latch.

In the chapter describing sequential circuit,John just list the characteristic equations in a table without even a word for explaination.It reads the equation of S-R latch is $$Q* = S + R' \cdot Q$$.

I thought it over and over,again and again with the conclusion that this equation is wrong.When both S and R are 1,Q*(the next state of Q) should be 0.However,according to this equation,$$Q* = 1 + 0 \cdot Q$$,we could calculuate that $$Q* = 1$$ which is obvious wrong.

After wikipediaed S-R latch,I found there is a condition $$S \cdot R = 0$$for this equation of High-Active S-R latch in http://books.google.com/books?id=4sX9fTGRo7QC&pg=PA344&lpg=PA344&dq=sr+characteristic+latch+equation&source=web&ots=9WdHN5uzTF&sig=ewGWuNX8g_4KozJuL5VyAS2yErc#PPA343,M1

So,My final question comes.Why does we need this condition for the equation?Why don't we just use $$Q* = S \cdot R' + R' \cdot Q$$ so that we could emit the condition $$S \cdot R = 0$$

MichealY.

#### steveb

Joined Jul 3, 2008
2,436
Hi, the book Digital Design,Principles and Practices 3e by John F. Wakerly frustrated me on the characteristic equation of S-R latch.

In the chapter describing sequential circuit,John just list the characteristic equations in a table without even a word for explaination.It reads the equation of S-R latch is $$Q* = S + R' \cdot Q$$.

I thought it over and over,again and again with the conclusion that this equation is wrong.When both S and R are 1,Q*(the next state of Q) should be 0.However,according to this equation,$$Q* = 1 + 0 \cdot Q$$,we could calculuate that $$Q* = 1$$ which is obvious wrong.

After wikipediaed S-R latch,I found there is a condition $$S \cdot R = 0$$for this equation of High-Active S-R latch in http://books.google.com/books?id=4sX9fTGRo7QC&pg=PA344&lpg=PA344&dq=sr+characteristic+latch+equation&source=web&ots=9WdHN5uzTF&sig=ewGWuNX8g_4KozJuL5VyAS2yErc#PPA343,M1

So,My final question comes.Why does we need this condition for the equation?Why don't we just use $$Q* = S \cdot R' + R' \cdot Q$$ so that we could emit the condition $$S \cdot R = 0$$

MichealY.
The SR latch does not traditionally allow the 11 input condition, so it doesn't matter what answer the equation gives for those inputs. However, if you want to consider specific SR latch circuitry that gives a well defined output for that input condition, you are free to use the appropriate equation that gives the answer for your device.

#### MichealY

Joined Apr 9, 2009
49

The SR latch does not traditionally allow the 11 input condition, so it doesn't matter what answer the equation gives for those inputs.
Why SR latch does not allow the 11 input condition?

MichealY.

#### steveb

Joined Jul 3, 2008
2,436

Why SR latch does not allow the 11 input condition?

MichealY.
I'm not 100% sure, but my guess is that the first devices that were made (many years ago) were unstable in that state. Since the device was simple and useful even without the 11 condition allowed, it persisted as a standard. Later designs may have a stable output for a 11 condition, but somehow the definition of an SR latch usually does not allow the 11 condition.

Hopefully, someone else here knows the history a little better and can verify or expand on this.

#### MichealY

Joined Apr 9, 2009
49
According to wikipedia and Digital Design Principles and Practices,condition 11 is usually avoided.Because,

1)Both of S and R simultaneously go down could led to metastablility problems or ringing(oscillate) state.
2)It breaks the rule Q = not QN.

MichealY

#### Papabravo

Joined Feb 24, 2006
12,695
The answer has to do with the propagation delay along the feedback paths and possibly which of the two commands arrived first. In addition to the fact that it is logically inconsistent to ask the device to "set itself" and "reset itself" at the same time. How would you resolve conflicting orders. Do people become metastable in that condition? Chuckling softly on that one.

#### MichealY

Joined Apr 9, 2009
49
The answer has to do with the propagation delay along the feedback paths and possibly which of the two commands arrived first.
Yes.In the book Digital Design,John says "Ofen but always,a commerical latch's specifications define "simultaneously"(e.g.,S and R negated within 20ns of each order.

In addition to the fact that it is logically inconsistent to ask the device to "set itself" and "reset itself" at the same time. How would you resolve conflicting orders. Do people become metastable in that condition? Chuckling softly on that one.
Papa,I could not understand this sentence.What's conflicting order?Do you simply mean conflict between "set itself" and "reset itself"?Could you explain it to me?Thanks.

Another question,
Why both S and R go down could led to metastable condition?
Why pulse shorter than minimum width applied to S or R could also led to metastable condition?What if compared with bitstable element?

MichealY.

#### Papabravo

Joined Feb 24, 2006
12,695
In the SR device there is only 1 output, labeled Q, and it should go to either the set state (Q = 1), or to the reset state (Q = 0). A digital ouput must be in one state or the other. It simply cannot go to both states simultaneously.

Metastability is a feature of real circuits. It occurs when a logic device cannot make up its mind what state it needs to be in. Setting S & R at the same time certainly sets up that condition.

#### MichealY

Joined Apr 9, 2009
49
In the SR device there is only 1 output, labeled Q, and it should go to either the set state (Q = 1), or to the reset state (Q = 0). A digital ouput must be in one state or the other. It simply cannot go to both states simultaneously.
Yes,but in reality,there is another state in which Q =1 and QN = 1.

Metastability is a feature of real circuits. It occurs when a logic device cannot make up its mind what state it needs to be in. Setting S & R at the same time certainly sets up that condition.
I could not argee with you.Only by setting S&R at the same time will not set up that condition.Only by setting S&R at the same time and then resetting S&R at the same time would may raise this condition.

It is because that the two NOR gate made up of the S-R latch maybe difference in speed.The Q gate maybe faster than QN gate,then the S-R latch will turn into set state,otherwise it will turn into reset state(this is some kind of race condition).So it is said that the state of S-R latchafter setting and then restting S&R at the same time is not determined.

But some textbook said "it is metastable or osciilate state".Why?Could you help me dig for more details.

And the second question 