Simple PEAK DETECTOR maxing out at 6 V

Thread Starter

Rogare

Joined Mar 9, 2012
78
Here is a circuit for a positive peak detector I have used many times. You could substitute a FET op-amp like LF-356. U2-B acts as a buffer so the voltage on the peak capacitor isn't drained off quickly. Using a smaller cap lets the circuit ramp up faster.
Thank you so much for this. It's now tested, built, and boxed, and so far it's working perfectly for my application!

At some point I'd like to figure out why my original circuit wasn't working, but in the meantime having a working circuit is terrific. Thanks again.
 

Thread Starter

Rogare

Joined Mar 9, 2012
78
Also, out of interest, here were the results of yesterday's troubleshooting on the original circuit design (before I implemented bountyhunter's suggestion):

Slew rate of op-amp to low?
Tried higher slew op-amps (TL072)—the output still maxed out at around the same point.

Insufficient output current?
Added output stage with NPN transistor (PN2222)—problem still there.

Capacitor too high?
Tried lower capacitors and though rise times were faster, the output was still maxing out.

Scope input impedance causing problems?
Added a really simple voltage follower stage, this didn't help (maybe it was too basic a design... just an op-amp with the inverting input and output shorted).

7660S/9V combination not able to deliver required current?
Tried replacing with 12V wall adapter... no improvement.

Duty cycle of signal too low?
Tried increasing duty cycle and no significant difference.
 

wayneh

Joined Sep 9, 2010
17,496
A lot might be revealed if you could get a 'scope on those measurements. The DC part of it is a mystery, so I suspect something wacky in the AC realm.
 

Ron H

Joined Apr 14, 2005
7,063
I think your sim is lying to you. There is a voltage drop across that resistor caused by the current to charge the cap up. So taking the tap to feed the input of the buffer op amp there will give a false high voltage while the op amp is charging the cap. I don't think that will help, I think it screws it up. The voltage at the cathode of D1 can significantly exceed the final voltage on the cap during the transition, so the output of the buffer will actually "overshoot" worse.
Some people are, IMHO, too quick to blame the simulator if it doesn't agree with their seat-of-the-pants analysis. I like to delve into the sim to see if there are subtleties that my intuition missed.

NOTE: The following discussion is about the attached schematic. I will refer to "your circuit" and "my circuit", although neither of them were invented by you or me.

In your circuit (k=0), the rising edge of the input pulse causes a large overshoot (limited by U1 max output current capability or saturation, depending on the value of R5) at the output of the first op amp, caused by the voltage drop across R5 as the cap charges. When the -input to U1 catches up to the +input (U2 output is at peak voltage), U1 output starts to drop, but the integrator action of R2 and the capacitance of D2 prevents it from instantly cutting off D1, so the cap continues to charge for a few microseconds. This effect can be minimized by reducing the value of R2 to 1k, but the held peak voltage still exceeds the input peak by a significant amount (in the sim, 115mV with a 10V pulse).

In my circuit (k=1), R5 allows the peak voltage to immediately reach the U2 output and feed back to U1, preventing the large overshoot at the U1 output. The cap does not get overcharged because there is no overshoot at U1, and therefore no R5/D2 integrator action. In the sim, the peak held voltage is within millivolts of the peak input voltage.

In my circuit (k=1), in order to get peak acquisition within one pulse width (PW), it is required that R5*C1 be much less than the pulse width (R5*C1<PW/10).

Attached is a plot of the significant waveforms for both circuits.
Obviously, I have no hardware to verify this analysis, but I sure would like to see how hardware performs. If I'm wrong, I want to know.

PS I tried the sim with BAS116 low-capacitance diodes. Your circuit and mine gave identical results at the output. There was overshoot and ringing at the U1 output, but to no detriment.
 

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Thread Starter

Rogare

Joined Mar 9, 2012
78
Haha. Actually, having someone (preferably in or near Toronto) who can be hired occasionally to make more advanced, good quality, well documented circuits to provided specs would be terrific. Pass it on. :)

I wanted to post the final circuit I ended up using, based closely on bountyhunter's design. So, here it is!
 

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Audioguru

Joined Dec 20, 2007
11,248
Hired? Near Toronto?
That is me.
I am retired and I can see downtown Toronto from my home in the suburbs.

Your 10M resistor parallel to the 10uF capacitor will take 1000 seconds (16.7 minutes) to discharge.
But the input bias current of the opamp will cause a voltage of up to 2.5V.
 

bountyhunter

Joined Sep 7, 2009
2,512
But the input bias current of the opamp will cause a voltage of up to 2.5V.
Yeah, I recommended an LF-356 way back on the first page of the thread.

Hired? Near Toronto?
That is me.
I am retired and I can see downtown Toronto from my home in the suburbs.
But can you see Russia from your front porch?:p

political humor, we have this election thing coming up and Sarah Palin is still making a fool of herself.
 

crutschow

Joined Mar 14, 2008
34,285
Some people are, IMHO, too quick to blame the simulator if it doesn't agree with their seat-of-the-pants analysis. I like to delve into the sim to see if there are subtleties that my intuition missed.

..............................
I completely agree with that. Often a simulation will show real subtleties or glitches in the circuit operation that I did not anticipate in the design. It's saved my behind more than once. Usually when the simulation is off, it is drastically off and it is readily apparent that there is a problem with the sim.
 

bountyhunter

Joined Sep 7, 2009
2,512
My minimal experience (31 years) was the reverse reflection of that: it was always somebody doing bench analysis that found the "subleties" the simulator missed and saved everybody's backside in the nick of time.

Personally, I always had too much work to do to waste time trying to debug the sim problems and figure out why it was lying. I just relied on actual bench data that picked up the things the people who were using sims missed.

Of course, the reason they could be fast and lazy and not do any actual bench work was because they knew there was somebody else coming along after them that would (me).

Sims had (have) a very narrow and specific usefulness in IC design and development. The main problem is they were useless at predicting any kind of stability criteria for either linear regs or switchers. Our problem was there was zero accountability in our design group to what they did so they just schlocked out functional silicon and ran for the hills leaving somebody else to debug it.
 

Ron H

Joined Apr 14, 2005
7,063
My minimal experience (31 years) was the reverse reflection of that: it was always somebody doing bench analysis that found the "subleties" the simulator missed and saved everybody's backside in the nick of time.

Personally, I always had too much work to do to waste time trying to debug the sim problems and figure out why it was lying. I just relied on actual bench data that picked up the things the people who were using sims missed.

Of course, the reason they could be fast and lazy and not do any actual bench work was because they knew there was somebody else coming along after them that would (me).

Sims had (have) a very narrow and specific usefulness in IC design and development. The main problem is they were useless at predicting any kind of stability criteria for either linear regs or switchers. Our problem was there was zero accountability in our design group to what they did so they just schlocked out functional silicon and ran for the hills leaving somebody else to debug it.
My minimal experience (40 years) included more breadboards than most engineers still working today will probably build in their lifetimes. For most of my career, simulators were either non-existent, or too clumsy and/or simplistic to be of any use. Today, many circuit design engineers are designing chips, where breadboards are next to worthless and simulations are the only way they can pretest their designs prior to initial silicon (I was one of them for a couple of years). My previous comment was aimed at seat-of-the-pants "mental" analysis (I called it intuition in that post). Simulators will either verify "intuition", or not. If the two are not in agreement, more analysis is called for.
One of these days, when I have the time, I'll breadboard that peak detector and prove my point.:eek:
 

bountyhunter

Joined Sep 7, 2009
2,512
Today, many circuit design engineers are designing chips, where breadboards are next to worthless and simulations are the only way they can pretest their designs prior to initial silicon
That's my point. Sims, at least the ones we had, are incapable of "pretesting a design". I never saw a level 1 (actual new product) work on first silicon for exactly that reason. Spin offs, clones, "sorta like it" had a better chance, but hardly ever happened either. The predictor of "working silicon" or silicon that needed only a minor tweak on the first pass was the knowledge and experience of the designer. Period, not any sim.

I have a real problem with sims, but a lot moreso with the mindsets of the people I kept running into who used them.

Idiot 1: "We have to have a Spice model for your (fill in any IC regulator) so we can verify the system." In other words, no electrons were used in the making of this brand new design. System level design being done by idiots who couldn't spell voltage regulator..... irate phone calls to follow.

Idiot 2: "We must have a value for Theta J-C for your voltage regulator."

I patiently explain a plastic SOT-223 device has no "case" as defined in thermal testing so the parameter Theta J-C is meaningless. He informs me I am not giving him customer service because the Spice model for our device (a model which we had nothing to do with) has a data line for Theta J-C and the simulation won't run without a number. So I make one up.

Take an inventory of the threads on this site. Count the number of "I ran the simulation and it doesn't work" versus "I built this circuit and it doesn't work". Go to the homework section. There is a two page thread running about making a single transistor amplifier with a gain of 50. Seriously. One transistor and four resistors and we have sims for something that would take five minutes to build.

We seem to be growing a generation of electrical engineers who are allergic to electrons.

My opinion of sims is not that they are completely worthless, it is that they should never be used unless the operator is smarter than the sim and knows where it's wrong..... and that honestly eliminates about 99% of the current users. They should never be used to bypass actual test data derived from building up something in the prototype form.

It reminds me of why I am not in favor of giving razor blades to small children: while I can not predict with 100% certainty exactly what they will do with them, history has shown me the chances are very high it will not yield a positive result.
 
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bountyhunter

Joined Sep 7, 2009
2,512
I reviewed your "sim plots" showing the overshoot. It appears it's about 3 us wide and only occurs if the input slews about 11v/3us (about 4V/us) or faster. It's so narrow I might not have ever seen it, if it does exist. Apparrently, the OP couldn't see it either especially since the op amps he is using can't slew fast enough to cause it to occur.

But here is the problem I see with the modification to my circuit you suggested:

You are taking the "output" at the top of the 100 Ohm resistor R5. Picture in your mind a very NARROW fast rise/fall time pulse, which is what peak detectors are designed to capture the PEAK value of (stored as the value across the cap).

As the pulse rises, the output of U1 is dumping max current (maybe 30 mA) into C1 to force it's voltage up which means there is a significant voltage drop across R5.

If you take the voltage where your circuit does, at the end of the input pulse (U1 output current stops flowing) there will be a significant voltage "step" down at the output as the voltage falls from the value of (cap voltage + Resistor drop) to just the cap voltage which is the stored peak reading.

If the output is the cap voltage (my design) there will be no down step in the peak value after the pulse passes.

There is also an inherent "undervalue" reading (from both designs) as the input pulses get shorter due to the voltage drop across the charging resistor and the cap not having enough time to fully charge. I believe taking the output from the cap will reduce the error because the feedback will keep telling U1 to keep sourcing current a little longer as the input pulse falls.

It's been 30 years since I did the design, but I remember that criteria (best accuracy reading short transients) was something I tested for and optimized because it was a peak level meter to detect when an audio amp was clipping. I believe if you test both connections reading the cap gives better fast transient accuracy as to actual peak value.
 
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Audioguru

Joined Dec 20, 2007
11,248
There is a two page thread running about making a single transistor amplifier with a gain of 50. Seriously. One transistor and four resistors and we have sims for something that would take five minutes to build.
Because the OP knows nothing about Ohm's Law nor about a single transistor amplifier.
He wrongly thought beta is the voltage gain.
If he built it with his wrongly calculated 50 ohm collector resistor then the transistor would have smoked and burned.

He probably does not have an oscilloscope like I did when I was young (I built it from a kit) and nobody had a simulation program then.
A simulation today would show him that his gain was far too high and maybe the transistor had asymmetrical clipping. It would also show the severe distortion without any negative feedback.
 

bountyhunter

Joined Sep 7, 2009
2,512
The thread is in the homework section so obviously the question came from an electronics student. I would logically assume the school had an Oscope and somebody who knew how to turn it on.... and possibly even a few transistors and resistors laying around, although I'm not sure schools even know what those are anymore.

And sometimes cooking a 10 cent transistor is a good way to learn.... I should know, I've cooked a few.

My point is that it doesn't bode well for the future of electronics when students get a simple assignment to build something and spend a week fiddling with a sim. And if the student actually "knows nothing" he needs to fix that problem by bugging his instructor.

Just my opinion.
 

Ron H

Joined Apr 14, 2005
7,063
My peak detector is designed to acquire the peak within the width of one pulse (100uS in this case), without overshoot except during acquisition (i.e., on the leading edge). This is accomplished by making RC<< pulse width, so that,by the end of the pulse, the cap is fully charged to the peak voltage (no current is flowing through the series resistor).

Moving the feedback to the cap results in overshoot which is held after the pulse ends, if the circuit is designed with the goal of single pulse peak acquisition. This is due to the lag in the feedback loop due to the RC time constant. If RC is not << pulse width, then single pulse peak acquisition cannot be accomplished, and the output will look nice and clean, but several (or many, in the OP's circuit) pulses will be required to acquire the peak voltage. If that is the goal, then this is the cleaner design.

Back to my circuit, where the peak is acquired in a single pulse: If the leading edge overshoot is undesirable, a second voltage follower can be added which buffers the cap voltage. This will be the peak hold output.

Bountyhunter, I totally agree that students should not have simulators, at least when unsupervised. Garbage in = garbage out.
BTW, I am not one of your aforementioned idiots.:D
 
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