Simple op-amp summing junction question

Thread Starter

Distort10n

Joined Dec 25, 2006
429
I posted this on USENET as well, but I figured the more minds who read it the better. Any thoughts?


This question arose from the typical "what do I do to protect an op-
amp when the input voltage is higher than supply?"

In a typical non-inverting configuration the answer seems straight
forward since the input will be at the non-inverting pin of the IC.
If the input voltage is higher than supply a simple series resistor to
current limit can be suitable in most cases.

With a typical inverting configuration things seem to be a bit more
nebulous. The voltage at the inverting pin of the IC will be held at
virtual ground (ideally) so a higher than supply input voltage coming
in on the input resistor does not immediately seem to be an issue.

I am trying to think of a way to violate this; i.e., make the voltage
at the summing junction be a diode drop higher/lower than either of
the supply voltages, and simulate in Spice. My configuration is as
follows:
Vcc = +5V
Vee = -5V
Rin = 10k
Rf = 3k
Vin = +15V
Vo = -4.5V

If I assume that the amplifier is in this state for a while the
summing junction would be ideally held at virtual ground. Now, if I
have a step input down to -15V, I am imagining that the output would
STILL be -4.5V for some period of time (ns, us). It will take a
period of time for the output of the amplifier to slew to the proper
output thus forcing the summing junction to virtual ground to make all
is well in the universe.

During this transient, I am calulating that the summing junction will
be ~-6.9V. This is more than a diode drop "lower" than the negative
supply rail thus turning on the internal ESD protection diodes so
input current limitation techniques must be used.

I am having trouble catching this in simulation. Perhaps I do not
have my sim set up correctly? I only see a transient of ~-1.3V which
is well within the supply rails.

Am I correct or am I all wet?


See attached for math derivation.
 

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hgmjr

Joined Jan 28, 2005
9,029
I wonder if the opamp model being used is modeling the opamp's negative input with a small amount of input capacitance and that prevents the voltage at the negative input from slewing to the expected negative 6.9V level before the opamp's output slew rate yanks it back to ground.

If this theory is correct then by scaling the two resistor values by a factor say 2 or even 10, you would see the negative excursion decrease with the applied negative input step.

hgmjr
 

Ron H

Joined Apr 14, 2005
7,014
I ran a simple sim on Linear Technology's SwitcherCAD III. The sim worked fine for me. The op amp model is a simple single-pole, 10MHz GBW amplifier. It doesn't have (or need) power rails.
A real op amp has input capacitance, which will reduce the size of the transient. Some also have diode clamps between the input pins.
You also need to make the input slew rate much higher than what the op amp's bandwidth and slew rate can handle.
 

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Thread Starter

Distort10n

Joined Dec 25, 2006
429
Boy did I misread the question.
You scared me for a second. I thought I had made a math error!:cool:

As to everyone else, thank you for your insights. From your responses and those on USENET I am glad I was actually on to something. The input capacitance of the op-amp is something that I honestly didn't take into account.

I will try it again and let you know the results tomorrow.
 
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