Hello,
I would just like to confirm something very simple, nontheless quite important.
I usually breifly look at timming signals in spec sheets but never really worried too much about them... until now.
I am running logic in an MCU at 10.5 MHZ as opposed to 10MHZ(which logic had no problems) and this seems to affect some timing signals which are used to bit bang a flash chip's control inputs.
I am using the M29W160EB70N6 flash memory chip. If someone can please goto page 22 of 40 of the spec sheet located at:
http://www.datasheetcatalog.org/datasheet/stmicroelectronics/9195.pdf
For example, the timming tag that we can look at is the "ELQV" which has a "max" time.
According to table 12 they are saying that the CE signal must go low for 70 ns before the valid data. Somehow the max/min convention is sort of confusing me.
Do they mean that the CE signal must go low and stay low for not longer than 70 ns...
****OR****
Do they mean that the CE signal must go low and stay low for atleast 70 ns or longer.
And the same thing goes for the "min" of the AVAV time which is 70 ns.
Do they mean that one valid address must last no longer that 70 ns...
****OR****
Do they mean that one valid address must last atleast 70 ns or longer...
All feedback to this question is sincerely appreciated.
Ross
I would just like to confirm something very simple, nontheless quite important.
I usually breifly look at timming signals in spec sheets but never really worried too much about them... until now.
I am running logic in an MCU at 10.5 MHZ as opposed to 10MHZ(which logic had no problems) and this seems to affect some timing signals which are used to bit bang a flash chip's control inputs.
I am using the M29W160EB70N6 flash memory chip. If someone can please goto page 22 of 40 of the spec sheet located at:
http://www.datasheetcatalog.org/datasheet/stmicroelectronics/9195.pdf
For example, the timming tag that we can look at is the "ELQV" which has a "max" time.
According to table 12 they are saying that the CE signal must go low for 70 ns before the valid data. Somehow the max/min convention is sort of confusing me.
Do they mean that the CE signal must go low and stay low for not longer than 70 ns...
****OR****
Do they mean that the CE signal must go low and stay low for atleast 70 ns or longer.
And the same thing goes for the "min" of the AVAV time which is 70 ns.
Do they mean that one valid address must last no longer that 70 ns...
****OR****
Do they mean that one valid address must last atleast 70 ns or longer...
All feedback to this question is sincerely appreciated.
Ross
Last edited:
