Hi,

in the image, my output signal becomes high when D flip flops comprise state1 AND when clock is active. That is some circuit is ANDed with clock signal and that makes output signal.

the problem is that when state 1 is switching to state 2 just short time when clock rises, the output signal becomes high again, and then immediately drops. But this rise is enough to switch some other shift register.....that is this output signal is then connected to shift register(clock pin).

I would drive all flipflops and register using same clock signal, but that wasn't how they proposed to do in textbook.

Textbook may be wrong, but I'm still trying to figure out if there is a way to make it like they did.

I saw they use input buffers(no explanations) and there are also IOPAD component library.
I'm using Lattise ISPLever software by the way.

so I though maybe I should use some buffers for that??? like input buffers? so that signals are aligned somehow? I actually don't know what "buffers" are all about.

Also I seen on internet smth like delays etc.. but can't find anything like that in ISPLever

the idea is to somehow delay calculation of output signal to give some time for clock and state flipflops to settle down....

any ideas, directions? is this possible at all?

 

Hello,

I cannot see the image you talk about. You can either use the "insert image" button on the Quick Reply area, or upload the image in the Go Advanced option.

 

attached image.

output_signal = state == 1 & clock is high.

the problem is the little bump when state is changing.
in the image I would like output signal to remain low.