Signal Delay Analysis of 3Bit Parallel Full-Adder in Multisim

Thread Starter


Joined Apr 23, 2012
Hello all,
This is my first post, I'm trying to simulate a laboratory project in Multisim but i'm encountering some problems:

1- The 7-segment display is not working properly, it only shows a zero.
2- Cannot figure out how to simulate and measure a signal delay (propagation delay) of the signal that passes from C-in to C-out (C means Carry Bit).

I've attached the full circuit that i'm using in Multisim & the lab report that me and my teammates wrote.
The report is already submitted, i'm not trying to get you guys to solve any assignment :), i simply hope to get some feedback on how to improve or fix the design of the simulation (i'm new to Multisim).

I have attached 3 pictures:

1-3bit adder 000000.png is without oscilloscopes & 7 segment display.
2-Signal Analysis Circuit Schematic.png is with oscilloscopes but without 7 segment display, the red line represents the path of the signal that has to be measured (delay).
3-3bit adder with 7 segment display.png is with oscilloscopes and 7 segment display.

I have attached 2 files :

1- .zip file contains the Multisim 11 Simulation.
2- .doc is the report.

Any feedback would be appreciated :)