Hi everyone,

From the attachment, the block diagram shows the architecture of New Synchronous Voltage to Frequency Converter. Currently I am reading it's paper and it says :

At each conversion, the integrator keeps a running total of its previous output and its current input. The output from the integrator is feed to a 1-bit analog/digital converter (ADC). This is simply a comparator with its reference input at a level of half the input range, 0V in this case.

The ADC output feeds a 1-bit digital/analog converter (DAC) which has output levels equal +Ur or -Ur. A summing amplifier completes the loop by summing the current input signal and the previous sample DAC output. The aim of the feedback loop is to try to maintain the average output of the integrator at the comparator reference level 0V.

Honestly, I am quite confuse with the explanations and here are my questions:

1) How does the DAC works in the circuit since the output of the D-flip flop is only 1 or 0 and not a range of binary numbers?

2) Why are there +Ur and -Ur at the DAC and how it works from the diagram? I do understand how DAC works but don't know how it works from the attached picture.

3) Aren't the output of the comparator become 1 when the output integrator is more than 0V (which is the reference level) and become 0 when integrator output is less than 0V? Why it does not show the correct waveform at the output of D flip-flop as shown in Figure 3c?

4) What's one shot (OS) and how it works?

Appreciate if anyone could answer my questions, really need to know this before I can proceed to further topics. Thank you.

 

Perhaps our Ebook material will explain better - http://www.allaboutcircuits.com/vol_4/chpt_13/9.html

 

Hi Beenthere,

Thanks for directing such an informative link. I have read about it and benefited a lot from there. From the attachment, if there any error in the waveform that was circled in blue? When there are 2 bits of 0 output from the flip-flop, aren't the slope of the waveform suppose to be positive twice instead of going up and down?

I do understand that the whole circuitry is 1-bit ADC. But from the explanation below, when we want to implement an ADC more than 1-bit, are we going to employ multiple integrator stages and comparator circuits in a cascode or cascade manner?

How would the 8-bit ADC with one time sampling do the same job as oversampled 1-bit ADC? Are the results of averaged digitized samples of 1-bit ADC same as one time sampled 8-bit ADC?

Variations on this theme exist, employing multiple integrator stages and/or comparator circuits outputting more than 1 bit, but one concept common to all ΔΣ converters is that of oversampling. Oversampling is when multiple samples of an analog signal are taken by an ADC (in this case, a 1-bit ADC), and those digitized samples are averaged. The end result is an effective increase in the number of bits resolved from the signal. In other words, an oversampled 1-bit ADC can do the same job as an 8-bit ADC with one-time sampling, albeit at a slower rate.

Thanks.....