# Shunt Capactive Compensation Load Power Factor

Discussion in 'Homework Help' started by jegues, Sep 21, 2011.

1. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
735
45
Did I do this correctly for the calculated quantities? Is this typical of what we would expect for a circuit like the following? Should the load angles be negative or positive?

The circuit is shown in pencil in the figure.

$\vec{V_{s}} = 80 < 0^{o} V$

• ###### Check.JPG
File size:
63.5 KB
Views:
39
Last edited: Sep 21, 2011

Mar 6, 2009
5,448
789

File size:
47.5 KB
Views:
19
3. ### t_n_k AAC Fanatic!

Mar 6, 2009
5,448
789
Also - it might make more sense if the 300Ω load were placed in series with the various capacitive reactances, rather than in parallel.

In that case, when Xc=171Ω one would expect to reach the unity power factor condition.

The load (300Ω) voltage in that case would just be

80*300/(471) or 50.96 V @ 0°

4. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
735
45
Thank you very much for all the comments tnk, they are very helpfull, but as a result I've got a few more questions.

See the new figure attached to this post for the circuit, and all the details that we are given. (It's not much)

NOTE: When they show 300//j171 the complex part is supposed to represent the parallel capacitor, in other words,

$300//-jX_{c}$

Where in the table, the values for Xc are given.

Isn't the power factor the $cos\theta$ where, $\theta$ is the angle of the load in question.

I.e.

$\theta = arg(\vec{Z}) = \frac{arg(\vec{V})}{arg(\vec{I})} = -19.95^{o} + 19.95^{o} = 0^{o}$

Hence,

$PF = cos\theta = 1$

Am I doing something incorrect here?

I can assure you it is.

Correct, but we aren't allowed to change the orientation of the circuit. (i.e. must be paralleled)

Everything you've mentioned so far has been helpful.

File size:
12.3 KB
Views:
26
5. ### t_n_k AAC Fanatic!

Mar 6, 2009
5,448
789
It's somewhat confusing that your hand drawn schematic sketch in the first post isn't the same as the schematic of figure L1-4. That's why I asked you to re-check the experimental schematic diagram.

As I look at the schematic in L1-4, I would interpret the load as being 300Ω||j171Ω. That is, a pure resistor of 300Ω in parallel with an inductive reactance of 171Ω ....??? I would also interpret the schematic to therefore include a parallel capacitive reactance of varying value - the point of the experiment.

You mention that

NOTE: When they show 300//j171 the complex part is supposed to represent the parallel capacitor, in other words,

$image=http://forum.allaboutcircuits.com/mimetex.cgi?300//-jX_%7Bc%7D&hash=e9d7db9680e52192ff44a802d2a846b4$

This is even more confusing. How could +j171Ω be equivalent to -jXc?

You also didn't seem to address my question which asked if the goal of adding parallel capacitance was to improve load power factor then why don't your results show an improvement. Your results show a worsening load power factor as the parallel reactance decreases [equivalent to increasing capacitance]. If no parallel capacitance gives the optimum power factor [unity] then why add capacitance at all?

If the load starts out being just 300Ω with nothing else in parallel then one would expect the current and voltage in the load to be in phase - since it's purely resistive. So the load itself would have "unity power factor". To my way of thinking this isn't the conventional purpose of assigning a power factor. Power factor is usually applied to the source conditions. Where the source current and voltage are in phase then one regards this as a unity power factor condition.

Values using my assumption would be

Last edited: Sep 26, 2011