Shift Register LED back-and-forth design problem

Thread Starter


Joined Nov 9, 2013
Hi everyone!

I am designing a "Knight Rider" circuit game for a final design project.

A single LED goes left and right repeatedly between 4 LEDs (this will eventually be 7 LEDs but I am struggling like crazy just testing with four). I can only use certain chips from the TTL 74LS family.

I've researched two ways to do this digital-logic only circuit:

1.) A bidirectional counter (74LS192), counting 0, 1, 2 and 3, then some type of gate/latch logic to toggle the up/down counter state.

2.) A bidirectional shift register (74LS194) and the same type of gate latch logic.

I'd love to use the shift register, as I score more points on my final design (and I want to learn about it anyway).

I stink at the gate latch logic, and need a gentle beating in the right direction.

I attached a Multsim 2001 screenshot with my "best" successful attempt.

The leftmost and rightmost LEDs feed into a two-input NOR gate (74LS02). That NOR gate's output feeds into the CLK input (negative-edge triggered) of a JK FF (74LS76). The JK FF's Q output feeds into the S0 Mode of the 74LS194 shift register.

I have the same leftmost-rightmost LED/NOR gate/JK FF logic feeding to the S1 Mode of the 74LS194 shift register.

The circuit works for a complete cycle, but the first JK Flip Flop (the one that initially sends the LED towards the right) holds high and doesn't toggle.

Holy Hannah, I am failing at this! I have scoured datasheets, looked at the Shift Register and FF worksheets on this forum, but I am missing something brain-dead simple!

Any gentle beatings in the right direction?

By the way, the Worksheets, this forum, and Derek Molloy's DCU Youtube videos have supplemented my coursework so well, thank you for doing all this!!!




Joined Sep 17, 2013
The only thing causing those FFs to toggle is the arrival of a 1 at QA or QD. I haven't followed the sequence through completely but it seems there will be a point where the register contains all 0s, so the FFs will no longer toggle.

Edit: If S0 and S1 both become 0 the register shifting will be inhibited.


Joined Mar 31, 2012
You are violating one of the cardinal rules of logic design. Never use asynchronous logic unless you have a damn good reason AND are willing to put in the effort needed to verify that the design cannot produce glitches on any clock signals and has no critical races.

Instead, run all of your clock inputs off of the same free-running clock signal and use logic to control what each chip does on each clock edge.

You need to approach this systematically. The first thing is to very explicitly determine exactly what you want the circuit to do. Create a table that has all of your desired states and shows what state they should move to next. Once you have that, then you will be in a position to start designing the logic to make that happen.

Thread Starter


Joined Nov 9, 2013
Thanks very much WBahn and Alec_t, I'll make sure I do synchronous clock pulses to the FFs, I'll make that table and re-approach this!