Just to note that those reset circuits only work with a high impedance reset input such as CMOS or most microprocessors provide. It has to be a lower impedance to reset TTL bipolar digital circuits.just as an example heres two reset circuits-on gives a hi going reset the other a low going reset
Texas Instruments show the typical and minimum output current from all their ordinary CD4xxx Cmos ICs and for their SN74HCxxxx high speed Cmos ICs.Just curious, what do you think will happen if the transition takes longer?
In the left circuit the capacitor is discharged by leakage currents at rest. When power is applied the capacitor takes time to charge by R1 so the transistor is turned off and its collector voltage is a logic high to reset a counter (if the counter needs a logic high for a reset).I am looking at sheldons schematics again and trying to figure out exactly how they work. But I am not that capable yet. Would someone please give an overview?
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