serial to parallel converter VHDL help

Thread Starter


Joined Dec 8, 2006
I have to project a serial to parallel converter that converts a serial bit Stream (Data_in) in a parallel signal of 8 bits (Data_out). The least significant bit, Bit_0, arrives by first and is shown by a high level on the First_bit signal (it always occurs every 8 Clock blows). When the new datum is ready it is necessary to raise the Data_out_valid signal for a Clock blow.

How can i do it?
where can i find the source code and a testbench for this circuit?

help me, thanks Francesca


Joined Nov 17, 2003
Have you tried to do anything on this project? In terms of "finding" source code you must be aware that once you find it you cannot pass it off as your own, so should look at writing the code yourself or don't bother - don't worry about testbenches, most programmes develop the testbench framework automatically which you can the populate with test parameters.

Anyway sounds like you are making a serial-in-parallel-out shift register, care to hazard a guess at what signals you think your model may require?