I'm just reading about BJTs for the first time but am a bit confused by the concept of saturation.

I think I understand how the \(V_{CE}\) vs \(I_{C}\) characteristic curve comes about. For a fixed base current, increasing the collector-emitter voltage from zero will gradually increase the collector current, until such time when the base-collector junction becomes reverse-biased. At this time, increasing the collector-emmiter voltage any further will not increase the collector current, since the maximum amount is already getting through. If you assume that the base-emmiter voltage is 0.7V, then the base-collector junction will become reverse-biased when the collector-emmiter voltage is 0.7V. For larger base currents you will get larger maximum collector currents, but the shapes of the curves will be the same. This image comes from the book i'm reading (Electronic Devices by Thomas Floyd):

Is my understanding correct so far?

The book states that saturation is the point at which the collector current has reached a maximum, so I assumed it was at \(V_{CE}=0.7V\), at the knee of each of the curves. But later in the book it elaborates a bit and says that saturation is usually below the knee of the curve, at a few tenths of a volt.

Now i'm confused and wondering if I'm not understanding things correctly at all? Could someone explain what saturation is and how it occurs? I'd be ever so grateful

Thanks!
epsilonjon

 

Saturation is when in a circuit the collector current cannot be increased more even if the base current increases.

 

Welcome to AAC.

It is a common misunderstanding with beginners that the BE and CE are somehow connected, especially given how the internal construction of the transistor is organized.

They aren't. It is possible to have much less than 0.1V on CE while having 0.6V drop on the BE. Transistors use quantum effects to achieve their function.

A general rule of thumb is you need at least 1/10 BE current to achieve guarenteed saturation.

Chapter 4: BIPOLAR JUNCTION TRANSISTORS

 

Let's look at it from a simple point of view. Usually, the base-emitter junction is forward biased and the base-collector junction is reverse biased. This leads to the straight lines in your plot. Now think about what happens if Vce=0.7 VDC. Well, the base emitter junction is forward biased and typically Vbe is 0.7 VDC. This leaves about 0 V for Vbc. Why? Because of Kirchoff's voltage rule that says the voltage drops around a loop add to zero. So, the the base-collector junction is right at the point where it will start to become forward biased if Vce drops to any lower value. This is why saturation must occur at a voltage below 0.7 VDC for Vce. even at Vce=0.6 V, the forward biasing is not yet allowing much base-collector current. But when Vce is 0.2 V or 0.3 V, the forward biasing produces significant current. So the saturation region is kind of a grey-area, where the base collector starts to become forward biased and the full saturation occurs when Vce is much lower than 0.7 VDC, with the actual value depending on the device, the drive current and the device temperature.

 

In a nutshell, "saturation" for a BJT is the point where a further increase in base current will not result in a corresponding increase in collector current. That's because Vce is as low as it's going to go for that particular Ic.

You might find it helpful to look at a few datasheets.
Here's OnSemi's datasheet for the 2N3904, an ubiquitous NPN small signal general purpose amplifier transistor:
http://www.onsemi.com/pub_link/Collateral/2N3903-D.PDF

Look on page 7 at Figure 16, "Collector Saturation Region".
Notice that the curves all stop when Ib=Ic/10; that's the generally accepted ratio to use when calculating the base current required for a desired collector current when using a transistor as a saturated switch.

Then look at figure 17, "ON Voltages". Note the Vbe(sat) curve, and the Vce curve.

When using a transistor as a switch, you want Vce to be low in order to minimize power dissipation in the transistor

 

I can clearly remember seeing this myself in an electronics practical as a teenager. It was a real "aha" moment: saturation was not the object of the exercise, but I had used far too low a base resistor so that's how it turned out.

It seemed reasonable for the collector to be low, but below the base!!! That is however how it works. Thinking of a transistor as being like a couple of resistors in series is not correct, and will lead to this kind of seeming impossibility

 

I think I am more confused now than ever

It is a common misunderstanding with beginners that the BE and CE are somehow connected, especially given how the internal construction of the transistor is organized. -
They aren't. It is possible to have much less than 0.1V on CE while having 0.6V drop on the BE. Transistors use quantum effects to achieve their function.

In my book it says \(V_{CB} = V_{CE} - V_{BE}\) which I understood to have come from Kirchoff's voltage law. Is this equation incorrect, or am I misunderstanding you?

Let's look at it from a simple point of view. Usually, the base-emitter junction is forward biased and the base-collector junction is reverse biased. This leads to the straight lines in your plot. Now think about what happens if Vce=0.7 VDC. Well, the base emitter junction is forward biased and typically Vbe is 0.7 VDC. This leaves about 0 V for Vbc. Why? Because of Kirchoff's voltage rule that says the voltage drops around a loop add to zero. So, the the base-collector junction is right at the point where it will start to become forward biased if Vce drops to any lower value. This is why saturation must occur at a voltage below 0.7 VDC for Vce. even at Vce=0.6 V, the forward biasing is not yet allowing much base-collector current. But when Vce is 0.2 V or 0.3 V, the forward biasing produces significant current. So the saturation region is kind of a grey-area, where the base collector starts to become forward biased and the full saturation occurs when Vce is much lower than 0.7 VDC, with the actual value depending on the device, the drive current and the device temperature

I understand that \(V_{CE}=0.7V\) is the point at which the base-collector junction changes bias. Below 0.7V and it is forward-biased; above 0.7V and it is reverse-biased. But I thought that the collector current becomes larger as the forward-bias decreases, reaching a maximum when it becomes reverse-biased? In terms of energy levels, this is the point at which the conduction band in the collector is completely below the conduction band in the base, so the maximum amount of collector current is being dragged through? This is what the characteristic curve shows at least?

You seem to be saying that a larger forward-bias across the base-collector junction (i.e. smaller \(V_{CE}\)) gives a larger collector current, but this is contrary to the characteristic curve, which is why I am confused.
-

In a nutshell, "saturation" for a BJT is the point where a further increase in base current will not result in a corresponding increase in collector current. That's because Vce is as low as it's going to go for that particular Ic.

So say I have a BJT in which the base-emmiter junction is forward biased and the base-collector junction is reverse biased, for some particular base current. If I now increase the base current, this will result in a larger collector current (\(I_{C}=\beta I_{B}\)) which will give a larger voltage drop across the resistor nearest the collector. Eventually this drop will become so large that the base-collector junction goes from reverse-biased to forward-biased. Is it at this point which further increases in the base-current do not equal further increases in the collector current? But won't this happen at \(V_{CE}=0.7V\), as in the analysis above?

 

A general rule of thumb is you need at least 1/10 BE current to achieve guarenteed saturation.

And some European transistors needs 1/20 th of collector current to saturate,like BC547 you will find these values in datasheet ,they give this parameter as VCE(SAT) Collector Emitter Saturation Voltage and VBE(SAT) Base Emitter Saturation Voltage.

Good Luck

 

But I thought that the collector current becomes larger as the forward-bias decreases, reaching a maximum when it becomes reverse-biased? ... This is what the characteristic curve shows at least?

Yes, correct.

You seem to be saying that a larger forward-bias across the base-collector junction (i.e. smaller \(V_{CE}\)) gives a larger collector current, but this is contrary to the characteristic curve, which is why I am confused.

No, not larger collector current, but larger base to collector current. The base to collector current flows in the opposite direction as collector current Ic. We mentioned Kirchoff's Voltage law above, but there is also Kirchoff's current law which says that all current flowing into the transistor equals zero. The collector current plus the base current flow in and these, when added, must equal the current flowing out of the emitter. (Ie=Ib+Ic) So, the saturation region is where some of the base current does not flow to the emitter and cause amplification, but instead it flows into the collector and gets wasted. The base current itself is small compared to the collector current, so the wasted current doesn't subtract all that much, but the wasted current will not be amplified, so it acts to saturate the current amplification.

So say I have a BJT in which the base-emmiter junction is forward biased and the base-collector junction is reverse biased, for some particular base current. If I now increase the base current, this will result in a larger collector current (\(I_{C}=\beta I_{B}\)) which will give a larger voltage drop across the resistor nearest the collector. Eventually this drop will become so large that the base-collector junction goes from reverse-biased to forward-biased. Is it at this point which further increases in the base-current do not equal further increases in the collector current? But won't this happen at \(V_{CE}=0.7V\), as in the analysis above?

Yes, and this is why the region of Vce<0.7 is the saturation region. But, the transistor equations say that the current in a forward biased junction is exponentially related to the voltage. So, very little forward bias current is flowing if Vce=0.6 V, as this is only a 0.1 V forward bias.

Let's run some typical numbers for a silicon diode. This applies for forward biasing if either the base-emitter, or the base-collector junctions.

I=Io*(exp(Vd/Vt)-1)

At room temperature, let's assume Vt=0.025 V and Io=1 pA. Under these conditions, a diode voltage of 0.1 V gives I=54 pA. Well, 54 pA is just a "flea's whisper" of a current.

Let's make a table.

Vd=0 V, I=0
Vd=0.1 V, I=54pA
Vd=0.2 V, I=3 nA
Vd=0.3 V, I=0.16 uA
Vd=0.4 V, I=8.9 uA
Vd=0.5 V, I=0.49 mA
Vd=0.6 V, I=26 mA
Vd=0.7 V, I=1.4 A
Vd=0.8 V, I=79 A

So, it's clear that Vce of 0.7 V (Vd=0), or Vce of 0.6 V (Vd=0.1 V) is not significantly into the saturation region. Hence, people are more interested in the practical point of saturation where significant base-collector current is flowing.

This may be a good point for you to look up the Ebers-Moll model of the transistor. It includes the exponential equations that describe both forward biasing and reverse biasing of both the base-collector and base-emitter junctions and can give you the characteristic curves in your plot. No model is perfect, but this one at least gives the DC performance of the transistor to reasonable accuracy and displays the basic functioning.

 

I think I am more confused now than ever

In my book it says \(V_{CB} = V_{CE} - V_{BE}\) which I understood to have come from Kirchoff's voltage law. Is this equation incorrect, or am I misunderstanding you?

I suspect you are taking this equation out of context, but as stated it is incorrect. The voltages are not related.

The BE is limited to the diode junction of the BE, while the CE is related to the gain of the transistor along with current through the base emitter.

The CE can drop 0 volts when the transistor is in saturation, while the BE drops 0.7 volts. This is a true statement, which violates what you refer to out of your text book. It does not violate Kirchoff's voltage law, because a transistor is an active device. A transistor has gain, and its characteristics are non intuitive. It has its own set of laws it obeys, because it is not a simple resistor.

I suspect you are referring to Ie = Ib + Ic for a transistor circuit. This is a true equation, and it is not about voltage. It doesn't come close to what you are attributing to Kirchoff's law.

It finally happened, I clicked edit instead of quote, and then modified the OPs post. Sorry about that, I think I put everything back the way it was.

 

I suspect you are taking this equation out of context, but as stated it is incorrect. The voltages are not related.

The BE is limited to the diode junction of the BE, while the CE is related to the gain of the transistor along with current through the base emitter.

The CE can drop 0 volts when the transistor is in saturation, while the BE drops 0.7 volts. This is a true statement, which violates what you refer to out of your text book. It does not violate Kirchoff's voltage law, because a transistor is an active device. A transistor has gain, and its characteristics are non intuitive. It has its own set of laws it obeys, because it is not a simple resistor.

Bill, no offense intended, but you need to rethink what you said here. Just about everything quoted above is incorrect. Transistor voltage drops are not related? Saturation voltage is zero volts? Kirchoff's law does not apply to active devices? Clearly these are erroneous statements.

 

Steveb, I think I understand a little better now.

So with reference to the characteristic curves (ignoring the numbers but just looking at the general shape):

For the low \(I_{B}\) curves, you should be able to attain the maximum "straight-line" collector current? It's only for large \(I_{B}\) curves that saturation occurs before the knee?

 

Steveb, I think I understand a little better now.

So with reference to the characteristic curves (ignoring the numbers but just looking at the general shape):

For the low \(I_{B}\) curves, you should be able to attain the maximum "straight-line" collector current? It's only for large \(I_{B}\) curves that saturation occurs before the knee?

I'm not sure I can answer that off the top of my head. My gut feeling us that it's all relative. If Ib is small then Vbe is smaller also. Let's say Vbe is only 0.4 V. Then the saturation region does not even start until Vce is less than 0.4 V. Then Vce needs to be even less than this to start stealing significant current from the base-emitter junction. Maybe it is straighter, or maybe it's all relative to scale. I'd have to run numbers and make plots to be sure. If I did so, I'd use the Ebers Moll model to get the answer. It's not really a question that comes up in practice, but it could be answered with certainty with a little effort.

 

I'm not sure I can answer that off the top of my head. My gut feeling us that it's all relative. If Ib is small then Vbe is smaller also. Let's say Vbe is only 0.4 V. Then the saturation region does not even start until Vce is less than 0.4 V. Then Vce needs to be even less than this to start stealing significant current from the base-emitter junction. Maybe it is straighter, or maybe it's all relative to scale. I'd have to run numbers and make plots to be sure. If I did so, I'd use the Ebers Moll model to get the answer. It's not really a question that comes up in practice, but it could be answered with certainty with a little effort.

I'm not really sure I understand the validity of the characteristic curves then. It's like they're usually incorrect? Why not draw them with the knee at the saturation CE voltage and the correct saturation collector current? Or more likely I am missing the point

 

I'm not really sure I understand the validity of the characteristic curves then. It's like they're usually incorrect? Why not draw them with the knee at the saturation CE voltage and the correct saturation collector current? Or more likely I am missing the point

I'm not sure if you are missing the point, but I think so. Also, I am missing your point. I don't understand what you are asking now.

I can say that the characteristic curves are correct and valid. The transistor will be operating somewhere on one of those curves. When the particular point of operation occurs where the base-collector becomes forward biased, the transistor is said to be in the saturation region. That's just a definition. Above the saturation region is the active region where the transistor acts like a good current source, or current amplifier.

There is no "one" saturation voltage, but the concept of saturation voltage is still useful to designers, and that saturation voltage is never at the knee, for the reasons I mentioned above. When you set up a transistor circuit, you can drive the transistor harder and harder, by increasing the Vbe, or Ib. Doing this moves the operation to a different curve. The transistor would like to provide more and more current and it will do so as long as Vce is large enough to let the transistor be at that point in the active region. However, if Vce becomes limited for some reason, the transistor operating point moves down the curve to lower Ic. The operating point will eventually move well below the knee of the curve if you keep pushing the Ib higher.

The reason why the saturation voltage tends to be considered a "number" is that the steep slope of characteristic curves in the saturation region makes the Vce relatively insensitive to the value of Ic. The operation basically gets pushed over as far as it can go, but it can't be pushed over all the way to Vce=0 because the slope in not straight up.

Basically, don't think about the knee as the saturation voltage. Think about the farthest point to the left on the characteristic curves for any value of Ic you wish have. So, the knee is like the upper limit of the saturation region, and the saturation voltage is like the lower limit of the saturation region. Both limits are important to circuit designers. The knee is the region that designers want to say away from when designing amplifiers and other linear circuits. Staying above the knee keeps you in the active region. However, when operating the transistor as a switch, the active region is to be avoided and the designer wants to either go all the way into full saturation, or all the way over the other way to cutoff, where the transistor is off.

 

Ahh okay. I was wrongly thinking that the collector current could not go larger than the saturation value, but it can go anywhere on the characteristic curve depending on how it's biased? So in this example:

What collector current will actually be reached? Somewhere above the saturation current but not as high as the 11.5mA?

But then I've confused myself again because if the collector current is larger the saturation current, then the voltage drop across the resistor will be larger and \(V_{CE}\) will be smaller, which goes against the characteristic curve?

Sorry to be a pain and keep asking questions which probably seem stupid, but I just really want to understand it and it's frustrating me!

Thanks once again for your help!

 

Ahh okay. I was wrongly thinking that the collector current could not go larger than the saturation value, but it can go anywhere on the characteristic curve depending on how it's biased? So in this example:

What collector current will actually be reached? Somewhere above the saturation current but not as high as the 11.5mA?

But then I've confused myself again because if the collector current is larger the saturation current, then the voltage drop across the resistor will be larger and \(V_{CE}\) will be smaller, which goes against the characteristic curve?

Sorry to be a pain and keep asking questions which probably seem stupid, but I just really want to understand it and it's frustrating me!

Thanks once again for your help!

Here the transistor can be at most barely in saturation, as the base current is not even 1/20 of Ic. Dividing the 9.8mA collector current assuming full saturation by the base current of 0.23mA would give a saturated gain of 42.6, which is a big saturated gain, 85% of normal.

The collector current clearly can't be more than 9.8mA (that is the value for full saturation here, restricted by the Vcc, 10kΩ, and VCE(sat). You cannot approach IC = βDC.IB in this case, let alone exceed it: you need to understand that, or you are missing the point. So Ic = 9.8mA, or perhaps a bit less.

That said what is Ic exactly? Some might suspect that the transistor operation may have merely passed out of the linear region to a point where the gain has been significantly depressed by the falling collector voltage, without truly saturating, and a significant further fall in Vce might be obtained with an increased base current. Here you need to be careful to follow whatever definitions your instructor requires to get credit for marked work: his definition counts, not mine.

The actual value of Vce achieved might (or might not) be less than Vbe - the value might best be found by simulation, if you had model data for the transistor, or in days of yore by drawing a 10V / 1kΩ load line on the transistor characteristic curves.

 

What collector current will actually be reached? Somewhere above the saturation current but not as high as the 11.5mA?

But then I've confused myself again because if the collector current is larger the saturation current, then the voltage drop across the resistor will be larger and \(V_{CE}\) will be smaller, which goes against the characteristic curve?

Sorry to be a pain and keep asking questions which probably seem stupid, but I just really want to understand it and it's frustrating me!

Thanks once again for your help!

First of all, you are not a pain at all. Second, your questions are not stupid but indicate that you are really trying to understand this very confusing concept that we all struggle with at first.

There is a reason why this seems confusing. Basically, you are using the wrong solution to determine if the circuit is in saturation. And you are correct to use the wrong solution, by the way. I did too. For example, look how I solved this.

I said that the base current equals (3V-0.7V)/10000=0.23 mA. Then I said that the collector current would be 50 times more, or 11.5 mA. Then I calculated the collector resistor voltage drop as 11.5 mA x 1 K= 11.5 V. Then I said, 11.5 volts is greater than my available voltage of 9.8 V, so it's in saturation.

So, I got the right answer by solving the problem incorrectly. The reason why we do this is because it's faster than trying to solve nonlinear equations precisely.

Anyway, the collector current reached will be the available voltage divided by the resistance in the path. The available voltage is 10V-0.2V=9.8V and the resulting current is 9.8 mA. In reality the saturation voltage may not be exactly 0.2 V, but the slight variations don't effect the answers very much, so we don't worry about it.

 

I am also reading the same book "Electronic Device" and have got exactly that confusion... Here is the original pic from the book that Epsilonjon referred to


and here would be the right value in my humble opinion

 

This guy gives a visual demonstration on his osciloscope of what happens as the transistor goes from cutoff through active region and then into saturation. This should make it very clear to see the actual voltages on the oscilloscope.

here is the link to his utube video.