Sample and Hold circuit

Thread Starter


Joined Jun 18, 2011
Hey i have designed a sample and hold circuit using a MOSFET with an input sinusoidal signal given to source and a clock signal of frequency greater than the frequency of sinusoidal signal (almost 4fs).This circuit is working well for a frequency of 100KHz however for higher frequencies of range 100MHz and 1GHz it is not working properly.Using this sample and hold circuit we have to build a high sampling rate Flash ADC.

any help on this work please

Thank you in advance



Joined Dec 26, 2010
For goodness' sake post a schematic. One might guess that gate-channel capacitance is cooking your goose for you, but how do you imagine anyone is going to be able to have more than vague ideas from a couple of sentences of description?