Sample and hold circuit simulation in Altium

hulage

Joined Nov 12, 2021
6
I'm done getting crap output signals. I've tried to simulate about a dozen circuits with several operational amplifiers. Filters work fine, but SAH doesn't. I give up and asking you for help. There can I find tutorials about designing circuits with OP AMPs? Also, if you got a circuit, you are welcome to post it)

Papabravo

Joined Feb 24, 2006
18,063
The shape of the v(out) [green] waveform should be a clue that the diode and the JFET are sometimes biased correctly and seem to work, sometimes they don't. I would question where that particular scheme came from and maybe spend a few minutes doing a bit of analysis on it. Whenever V(in) is less than about 2.0V you have a follower, and when V(in) is greater than 2.0V you have your sample and hold action. My conclusion is that you need a better circuit that works for all values of V(in).

In order to turn off a depletion-mode JFET off, you must make the gate terminal more negative than the source terminal by some threshold amount. consult the datasheet for accurate numbers. The following simulation is conceptually what you want, but I am unable to quickly identify a suitable JFET, or inded any FET with a suitably low Rds(on) which is critcal to making this scheme work. I have used a negative voltage source V2, for the specific condition that there is a suitable JFET and we want the gate to be 10 volts below the minimum value of V(in).

crutschow

Joined Mar 14, 2008
29,463
Why are you using a sinewave to control the FET?
It should be a pulse to sharply turn the FET on and off.

Papabravo

Joined Feb 24, 2006
18,063
Why are you using a sinewave to control the FET?
It should be a pulse to sharply turn the FET on and off.
If you look vey carefully at his graph you can see v(ctrl) in the rust brown color, is in fact a series of pulses. They just happen to be the wrong polatity for a JFET relative to the input sinwave. The pulses only turn the FET on after overcoming the diode drop and the gate goes negative with repect to the source. The graphic in the schematic is misleading. I think all voltage generators in altium are called VSIN, but since I'm not familiar with that package I could be FOS.

The FET is also backwards between the two amplifiers, The source should be connected to U2 and the drain to U1. Otherwise the source willbe connected to the capacitor which is definitely NOT what you want.

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hulage

Joined Nov 12, 2021
6
I only got this circuit workring. But it's track and hold. And inverting. And there is a lot of noise.
The same OP AMPs are not working in previous circuit i shared(
The following simulation is conceptually what you want, but I am unable to quickly identify a suitable JFET, or inded any FET with a suitably low Rds(on) which is critcal to making this scheme work.
Thanks) It's time for me to look for suitable specs in datasheets.
Also, how to transfom attached circuit to non-inverting, sample and hold, low noise circuit?

hulage

Joined Nov 12, 2021
6
Here I tried to build track and hold
I attached capacitor sweep analysis from 1pF to 1nF. It shows, that the problem is not in cap

DickCappels

Joined Aug 21, 2008
8,668
You are not paying attention to the advice you are given. You are not going to have the sample & hold that you seek until you start driving the JFET with a series of gating pulses of the proper polarity. A sine wave, you may notice, will not work correctly to control the sampling by the JFET.

hulage

Joined Nov 12, 2021
6
You are not paying attention to the advice you are given. You are not going to have the sample & hold that you seek until you start driving the JFET with a series of gating pulses of the proper polarity. A sine wave, you may notice, will not work correctly to control the sampling by the JFET.
JFET is driven by pulse signal, Altium just shows it like sinusoidal. You can see it on the both attached graphs

DickCappels

Joined Aug 21, 2008
8,668
Did you see what Papabravo said in post #2 about a JFET being a depletion mode device? Drive the source from your opamp instead of the drain and use a resistor (10k and up depending upon pulse width) to bring the gate voltage back to the source voltage when the pulse is gone. You should be careful to not draw gate current (forward bias the gate) lest it show up in your output.

Please turn your diode around so that it actively shuts off the JFET rather than driving the gate positive. (You had it the right way in Post #1).