Hello Guys,

I have a question on macro model of MCP6000 series op amps. In the attachments, you may find the schematic of my circuit and results taken with pspice. My question is that when I use the macro model that belongs to MCP6001, my low pass filter shows a result like it is a high pass circuit. If I use the simplified model of MCP6xxx series, the result is like how it is expected. Does anyone have problem like this before? Is it the macro model or my circuit? In addition, when I check the voltage clamp which is there to protect from over voltage conditions, it does not clamp the voltage at 3.3 +VDon. Could you explain why ? Is this because of the pspice ?

This circuit is to receive analog signals from 0-5V sensor output for 3V ADC so 2M&3M resistors are voltage dividers.

Thank you in advance.

 

Doesn't look like a Sallen-Key filter topography. Normally for the unity DC gain version, the non-inverting input is driven with the amp configured as a unity gain non-inverting amplifier with direct feedback from the output to the inverting input.

See figure 2 here ...http://en.wikipedia.org/wiki/Sallen%E2%80%93Key_topology

 

Corrected schematic is in the attachment.

 

I don't think it's Pspice or the models. Your op amp has only a single supply with zero bias on the input. You can't pass an AC signal through such a connection. since half the signal goes below ground. You need to bias the input signal at 1/2 of Vcc, at least for any AC simulations.

Also clamping and other large-signal effects are not modeled in AC analysis which uses a small-signal model. You need to do a transient analysis to simulate the clamp.

What is the waveform of the sensor output?

 

Thank you for the useful information AC analysis of such connection like this. As for the voltage clamp, yes I tried to observe it by using the transient analysis but didn't work.

The sensor is a position sensor so the output is not a rapid signal.

 

Thank you for the useful information AC analysis of such connection like this. As for the voltage clamp, yes I tried to observe it by using the transient analysis but didn't work.

....................

What do you mean it "didn't work"?

Post your simulation.

 

What do you mean it "didn't work"?

Post your simulation.

What I meant is that the voltage at node 2 (see the annotated schematic in the attachment) was not clamped at 3.3V+Vd(on) when the input voltage goes above 3.3V . This is why the clamp is there to protect circuit from a voltage level above 3. You can see the result in the attachment. I applied 7V sin signal at input and after the divider input voltage is 4.2V and at this level clamp should take place and limit the voltage at 3.3+Vd(on), am I right?

This is the ciruit file you may wanna take a look:


Vin 1 0 SIN 0 7 1


*Voltage Divider Section
Rd1 1 2 2M
Rd2 2 0 3M

*Voltage Clamp Section
D1 2 6 BAT54
D2 0 2 BAT54

*Butterworth Filter
R1 2 3 10K
C1 3 5 0.022U
R2 3 4 10K
C2 4 0 0.010U
X1 4 5 6 0 5 MCP6xxx

.MODEL BAT54 D(
+ IS = 2.117E-07
+ N = 1.016
+ BV = 36
+ IBV = 1.196E-06
+ RS = 2.637
+ CJO = 1.114E-11
+ VJ = 0.2013
+ M = 0.3868
+ FC = 0
+ TT = 0
+ EG = 0.69
+ XTI = 2)

.TRAN 500u 1000m 0 500u UIC
.PROBE
.END

Thank you in advance.

 

I don't see any 3.3V supply in your circuit file.

 

I did copy and paste and it was defined above where Vin defined.

VCC 6 0 3

and hold on I have results for you

 

So far I guess it is the macro model I repeated the simulation with a different opamp from TI, OPA342

The results are attached. It works how it is supposed to work with OPA342.

 

I'd agree your original macro model is a dud.

By the way - your frequency response with the voltage divider included would presumably be quite different when comparing the relative levels from the actual input to the filter output - the input being the top of the voltage divider. That is from node 1 to 5.

What you show appears to be the relative gain response from node 2 to 5.

 

BTW - You make no mention of the voltage clamping issue when using the alternative macro model. What happened?

 

Still shows 4.2V at node 2 in transient analysis. Dunno what goes wrong.

 

Can you probe node 6 to ascertain that the top diode cathode actually "sees" 3.3V?

 

Yes, it does.

 

Then it would appear there's also something wrong with the diode model.

 

Well, I figured that out. The thing is that, in the voltage divider section I placed "M" to determine these are megaohm resistors but pspice uses "MEG" for mega. So when I use "M", the resistors are miliohm resistors and current flow over the diode becomes 850amps. This is a way above the max forward current and the simulation gives unexpected results. I replaced M with MEG and that solved it.

Thank you all, for your helpful comments, I appreciate it.