Hello,
I'm using a binary ripple counter with the clock input signal and the divide by 64 signal (from the counter) running into an AND gate. The problem is that because it's a ripple counter the propogation delay for the divide by 64 signal adds up to about 150ns, thus causing a race condition at the and gate. I was wonder if there are any cheap simple ways to correct this. I could use a Low pass filter to delay the signal a little,but i want to procuce a few of these and the duty cycle on each will by slightly different because of the variance in the switching threshold on the gates. I've also messed around with all pass filters a little, but havent had much success.
Thanks
I'm using a binary ripple counter with the clock input signal and the divide by 64 signal (from the counter) running into an AND gate. The problem is that because it's a ripple counter the propogation delay for the divide by 64 signal adds up to about 150ns, thus causing a race condition at the and gate. I was wonder if there are any cheap simple ways to correct this. I could use a Low pass filter to delay the signal a little,but i want to procuce a few of these and the duty cycle on each will by slightly different because of the variance in the switching threshold on the gates. I've also messed around with all pass filters a little, but havent had much success.
Thanks