Ref: Ripple Adders and CLA
Hello All,
First post from newbie. I have been trying to learn about the propagation delays for Full Ripple adders and Carry Look Ahead adders. I would very much appreciate if someone could confirm that I have understood the correctly.
For a 4-bit full ripple adder, there is a maximum propagation delay of 9 gates, in general the formulae is 2(n + 1). I have attached a picture of a 4-bit adder showing the 9 gates.
http://img188.imageshack.us/img188/8210/ripplej.jpg
For a 4-bit Carry Look Ahead adder, the carry in does not propagate through all the gates, instead is estimated due to the propagate and generate minterms.
For a 4- bit CLA the maximum gate delay is 4, as that is the most time consuming. Again I have attached a picture showing the 4-bit CLA.
http://img52.imageshack.us/img52/2483/clag.jpg
My question is that although I have been told it is 4 gate delay at max, I guess that is because we are assuming all inputs Ai, Bi and Cin will be present simultaneously, therefore those delays are mirrored at every stage. The only difference is the ones required to generate the carry. C3 being the longest.
So is it a 4 gate delay for a 4-bit CLA. Is there a general formula for calculating the propagation delay for higher order inputs e.g. 8-bit?
Thank you in advance for your help.
Jag.
Hello All,
First post from newbie. I have been trying to learn about the propagation delays for Full Ripple adders and Carry Look Ahead adders. I would very much appreciate if someone could confirm that I have understood the correctly.
For a 4-bit full ripple adder, there is a maximum propagation delay of 9 gates, in general the formulae is 2(n + 1). I have attached a picture of a 4-bit adder showing the 9 gates.
http://img188.imageshack.us/img188/8210/ripplej.jpg
For a 4-bit Carry Look Ahead adder, the carry in does not propagate through all the gates, instead is estimated due to the propagate and generate minterms.
For a 4- bit CLA the maximum gate delay is 4, as that is the most time consuming. Again I have attached a picture showing the 4-bit CLA.
http://img52.imageshack.us/img52/2483/clag.jpg
My question is that although I have been told it is 4 gate delay at max, I guess that is because we are assuming all inputs Ai, Bi and Cin will be present simultaneously, therefore those delays are mirrored at every stage. The only difference is the ones required to generate the carry. C3 being the longest.
So is it a 4 gate delay for a 4-bit CLA. Is there a general formula for calculating the propagation delay for higher order inputs e.g. 8-bit?
Thank you in advance for your help.
Jag.
