Woot, questions time!
Ring oscillators require you to have an odd number of NOT gate stages, it's obvious why, HOWEVER, the exception is one. You can't have a ring oscillator with only 1 stage. Why is this? I figure it's probably because the circuit has a stable state at some point, but how/why? I heard somewhere on this forum that it DOES actually oscillate, but I have tested it with no measurable oscillation (I use a single transistor per NOT stage). A little mathematical explaination would be nice, especially if you can explain it intuitively as well. Also, what determines the rise/fall times of the resulting oscillations? Usually I've been using schmitt triggers to speed it up, but what can I do to help improve it without the triggers? I've used several extra buffer stages, and that helps a little, but it's just not enough for me.
Will having poor rise-fall times effect my digital circuits? If so, in what way and why?
What parasitic characteristics (Capacitance, inductance, etc; ) should I consider in high-frequency digital BJT circuits? Is there an equivalent circuit diagram I could use? It seems that these parasitic characteristics are keeping me from getting fast clocks and fast logic gates from my BJTs (Mainly 3904s and 3906s). What "tricks" could I use to quicken their trasition times, and why do these tricks work? Low-power is also in my interest, for the extra challenge I would like to make my circuit as low-power as possible, but that's really just tertiary.
Ring oscillators require you to have an odd number of NOT gate stages, it's obvious why, HOWEVER, the exception is one. You can't have a ring oscillator with only 1 stage. Why is this? I figure it's probably because the circuit has a stable state at some point, but how/why? I heard somewhere on this forum that it DOES actually oscillate, but I have tested it with no measurable oscillation (I use a single transistor per NOT stage). A little mathematical explaination would be nice, especially if you can explain it intuitively as well. Also, what determines the rise/fall times of the resulting oscillations? Usually I've been using schmitt triggers to speed it up, but what can I do to help improve it without the triggers? I've used several extra buffer stages, and that helps a little, but it's just not enough for me.
Will having poor rise-fall times effect my digital circuits? If so, in what way and why?
What parasitic characteristics (Capacitance, inductance, etc; ) should I consider in high-frequency digital BJT circuits? Is there an equivalent circuit diagram I could use? It seems that these parasitic characteristics are keeping me from getting fast clocks and fast logic gates from my BJTs (Mainly 3904s and 3906s). What "tricks" could I use to quicken their trasition times, and why do these tricks work? Low-power is also in my interest, for the extra challenge I would like to make my circuit as low-power as possible, but that's really just tertiary.