I'm looking at the current arrangement of memory in my updated design, and realized something:
1) the RAM on the logic board is an MC6810, is only 128 bytes, and a long-obsolete and well-sought after part (apparently some pinball machines use this particular RAM chip as well).
2) the RAM on the interface board is a 6116, has a capacity of 2K bytes, of which only 128 bytes are used, and is still a 'common' part.
I would like to be able to tweak the partial address decoding such that I can use the 6116 for both address ranges without having to rewrite the firmware (if I can't find some NOS SC44125s, I may have to respin the board to use an HC11 variant instead... might as well address the RAM at the same time).
The attached picture contains all the existing 'glue logic' address decoding, address ranges called up by the firmware, etc.
I have a general idea what I need to do for the RAM equation (and which would involve adding a NAND and XOR gate to the RAM decode line), but want to see if the brain trust can see any equally workable approaches.
1) the RAM on the logic board is an MC6810, is only 128 bytes, and a long-obsolete and well-sought after part (apparently some pinball machines use this particular RAM chip as well).
2) the RAM on the interface board is a 6116, has a capacity of 2K bytes, of which only 128 bytes are used, and is still a 'common' part.
I would like to be able to tweak the partial address decoding such that I can use the 6116 for both address ranges without having to rewrite the firmware (if I can't find some NOS SC44125s, I may have to respin the board to use an HC11 variant instead... might as well address the RAM at the same time).
The attached picture contains all the existing 'glue logic' address decoding, address ranges called up by the firmware, etc.
I have a general idea what I need to do for the RAM equation (and which would involve adding a NAND and XOR gate to the RAM decode line), but want to see if the brain trust can see any equally workable approaches.
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