# Resistively-loaded MOS Differential Amplifier Design

#### mosfetmike

Joined Apr 19, 2013
6
Hello, I am attempting to design a resistively-loaded differential pair amplifier.

The specs are listed below:

1. Power consumption < 50 mW
2. Differential gain = 20 dB
3. Input common mode range = 5 to 9 V
4. VDD = 12 V

As you can see in the attached circuit drawing, the only parameters that I have to design are the current source Ibias and the offset voltage of the inputs.

My attempt at the solution is shown below:

Gain = 20 dB ==> 10 V/V
Get 5 V/V from each side of diff pair

A = gm(R1||ro1) = 5 V/V
A = gm(10k||54.47k) = 5 V/V
gm = 0.592 mA/v

I = (gm)^2 / (2*kn) = (0.592mA/V)^2 / (2*0.5934) = 0.295 mA = 0.3 mA

Ibias = 2*I = 0.6 mA

Now I attempt to determine the offset voltage for the inputs.

1. To be in saturation, Vds > Vgs - Vt
2. Therefore Vd > Vg - Vt
3. Then Vg < Vd + Vt
4. Vd = VDD - I*R1 = 12V - (.3mA)(10k) = 12V - 3V = 9V

Then from (3), Vg < Vd + Vt
Vg < 9 V + .7 V = 9.7 V

So Vg, the gate voltage of U4, must be less than 9.7 V.
I choose 6.7 V for the gate voltage to get well below the edge of saturation.

This is what I have so far. I then attempt to do a DC sweep analysis to find the transfer characteristic of (VO2-VO1) vs (VINP - VINN). Once I have the transfer characteristic, I will find the maximum linear region and compute the DC gain.

My problem is that I am not sure my procedure for doing the DC sweep of a differential amplifier is correct. I have attempted to use a parameter Vbias (as can be seen in the circuit) to sweep both input offset voltages simultaneously. The waveform I get though after placing a probe at one of the amplifier's outputs shows that the input offset bias should be around 3.5 V (in the linear region), which was not what I calculated (~6.7 V).

Any help regarding whether my calculations are wrong or whether I am doing the DC sweep incorrectly to find the transfer characteristic would be greatly appreciated.

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