Hi there, I am using the CD4094BE SIPO shift register for a project of mine (I am an EE student), and i have this issue that when
data is low and i am giving 1 CP Q1-Q8 all turn to logic low instead of just shifting one LOW to Q1.
when shifting HIGH all is working well, my only problem is when data is low and CP is given all OUTPUTS turn LOW at once.
I tried reducing the CAP on the CK line to 22nF and add a 100nF decoupling cap near the IC still no luck... both schematics are attached here, please help!
data is low and i am giving 1 CP Q1-Q8 all turn to logic low instead of just shifting one LOW to Q1.
when shifting HIGH all is working well, my only problem is when data is low and CP is given all OUTPUTS turn LOW at once.
I tried reducing the CAP on the CK line to 22nF and add a 100nF decoupling cap near the IC still no luck... both schematics are attached here, please help!
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