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register file in verilog

Discussion in 'Programmer's Corner' started by TheRekz, Jan 25, 2010.

  1. TheRekz

    Thread Starter New Member

    Oct 25, 2009
    13
    0
    I am asked to implement a register file in verilog, such as in the following drawings, can someone please tell me what components I need inside?

    [​IMG]
     
  2. swinch

    New Member

    Jan 24, 2010
    5
    0
    Hi,
    I did something a uni with registers awhile a go on a Spartan 3 FPGA development board.
    Basically there was a data in, data out, write enable, address line, a switch input and a couple other display lines (LEDs etc).
    The idea was to build a microcontroller on a FPGA as the lab work of a course. Anyway we used Xilinx to build a Data_RAM block.
    I've attached the code for the register we did, hopefully its helpful to you :)


    Code ( (Unknown Language)):
    1.  
    2. entity REGISTERS is
    3.     Port ( LEDs : out  STD_LOGIC_VECTOR (7 downto 0);
    4.            switches : in  STD_LOGIC_VECTOR (7 downto 0);
    5.            SSD_cont : out  STD_LOGIC_VECTOR (15 downto 0);
    6.            reg_addr : in  STD_LOGIC_VECTOR (7 downto 0);
    7.            reg_din : in  STD_LOGIC_VECTOR (7 downto 0);
    8.            reg_we : in  STD_LOGIC;
    9.            reg_dout : out  STD_LOGIC_VECTOR (7 downto 0);
    10.            clk : in  STD_LOGIC;
    11.            reset : in  STD_LOGIC);
    12. end REGISTERS;
    13. architecture Behavioral of REGISTERS is
    14. signal dout :std_logic_vector(7 downto 0);
    15. begin
    16. DataRAM : entity work.Data_RAM
    17.         port map( clk =>clk,
    18.             addr=>reg_addr,
    19.             we=>reg_we,
    20.             din=>reg_din,
    21.             dout=>dout
    22.             );
    23. --Special Funcion Register Mapping --
    24. MAP_WRITING: process(clk, reg_we, reset)
    25. begin
    26.     if(reset ='1') then
    27.         LEDs <=X"00";
    28.         ssd_cont<=X"0000";
    29.     elsif(rising_edge(clk) and reg_we ='1')then
    30.         if(reg_addr = X"00")then
    31.              LEDs<=reg_din;
    32.         elsif(reg_addr = X"02") then
    33.             ssd_cont(7 downto 0) <= reg_din;
    34.         elsif(reg_addr = X"03") then
    35.             ssd_cont(15 downto 8) <= reg_din;
    36.         end if;
    37.     end if;
    38. end process;
    39. MAP_REDAING : process(reg_addr, switches, dout)
    40. begin
    41.     if(reg_addr = X"01") then
    42.         reg_dout <= switches;
    43.     else
    44.         reg_dout <= dout;
    45.     end if;
    46. end process;
    47. end Behavioral;
    48.  
     
  3. TheRekz

    Thread Starter New Member

    Oct 25, 2009
    13
    0
    why do you need the LED for? Is this in verilog? as the syntax seems a bit different from what I learned
     
  4. Papabravo

    Expert

    Feb 24, 2006
    12,285
    2,725
    That's because it is VHDL!
     
  5. TheRekz

    Thread Starter New Member

    Oct 25, 2009
    13
    0
    I have the following code:

    Code ( (Unknown Language)):
    1.  
    2. module RegisterFile(ReadRegister1, ReadRegister2, WriteRegister,
    3. WriteData, RegWrite, Clk, ReadData1, ReadData2);
    4.  
    5. input [4:0] ReadRegister1, ReadRegister2; // Two registers to be read
    6. input [4:0] WriteRegister; // Register address to write into
    7. input [31:0] WriteData; // Data to be written into WriteRegister
    8. input RegWrite; // RegWrite control signal. Data is written only when this signal is enabled
    9. input Clk;
    10. output [31:0] ReadData1, ReadData2;
    11. reg [31:0] RF [31:0];
    12.    
    13. always begin
    14. // write the register with new value if Regwrite is high
    15.  
    16. @(negedge Clk)
    17. begin
    18. assign ReadData1 = RF[ReadRegister1];
    19. assign ReadData2 = RF[ReadRegister2];
    20. end
    21.    
    22. @(posedge Clk)
    23.  if (RegWrite)
    24.     RF[WriteRegister] <= WriteData;
    25.    
    26. end
    27.  
    28. endmodule
    29.  
    30.  
    what is wrong with the syntax here ? it has to do with the negedge and the assign... What I want to do here is assign ReadData 1 and 2 to a data on a negative clock edge
     
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