register file in verilog

Thread Starter

TheRekz

Joined Oct 25, 2009
13
I am asked to implement a register file in verilog, such as in the following drawings, can someone please tell me what components I need inside?


 

swinch

Joined Jan 24, 2010
5
Hi,
I did something a uni with registers awhile a go on a Spartan 3 FPGA development board.
Basically there was a data in, data out, write enable, address line, a switch input and a couple other display lines (LEDs etc).
The idea was to build a microcontroller on a FPGA as the lab work of a course. Anyway we used Xilinx to build a Data_RAM block.
I've attached the code for the register we did, hopefully its helpful to you :)


Rich (BB code):
entity REGISTERS is
    Port ( LEDs : out  STD_LOGIC_VECTOR (7 downto 0);
           switches : in  STD_LOGIC_VECTOR (7 downto 0);
           SSD_cont : out  STD_LOGIC_VECTOR (15 downto 0);
           reg_addr : in  STD_LOGIC_VECTOR (7 downto 0);
           reg_din : in  STD_LOGIC_VECTOR (7 downto 0);
           reg_we : in  STD_LOGIC;
           reg_dout : out  STD_LOGIC_VECTOR (7 downto 0);
           clk : in  STD_LOGIC;
           reset : in  STD_LOGIC);
end REGISTERS;
architecture Behavioral of REGISTERS is
signal dout :std_logic_vector(7 downto 0);
begin
DataRAM : entity work.Data_RAM
        port map( clk =>clk,
            addr=>reg_addr,
            we=>reg_we,
            din=>reg_din,
            dout=>dout
            );
--Special Funcion Register Mapping --
MAP_WRITING: process(clk, reg_we, reset)
begin
    if(reset ='1') then
        LEDs <=X"00";
        ssd_cont<=X"0000";
    elsif(rising_edge(clk) and reg_we ='1')then
        if(reg_addr = X"00")then
             LEDs<=reg_din;
        elsif(reg_addr = X"02") then
            ssd_cont(7 downto 0) <= reg_din;
        elsif(reg_addr = X"03") then
            ssd_cont(15 downto 8) <= reg_din;
        end if;
    end if;
end process;
MAP_REDAING : process(reg_addr, switches, dout)
begin
    if(reg_addr = X"01") then
        reg_dout <= switches;
    else
        reg_dout <= dout;
    end if;
end process;
end Behavioral;
 

Thread Starter

TheRekz

Joined Oct 25, 2009
13
I have the following code:

Rich (BB code):
module RegisterFile(ReadRegister1, ReadRegister2, WriteRegister,
WriteData, RegWrite, Clk, ReadData1, ReadData2);

input [4:0] ReadRegister1, ReadRegister2; // Two registers to be read
input [4:0] WriteRegister; // Register address to write into
input [31:0] WriteData; // Data to be written into WriteRegister
input RegWrite; // RegWrite control signal. Data is written only when this signal is enabled
input Clk;
output [31:0] ReadData1, ReadData2; 
reg [31:0] RF [31:0];
    
always begin
// write the register with new value if Regwrite is high

@(negedge Clk)
begin
assign ReadData1 = RF[ReadRegister1];
assign ReadData2 = RF[ReadRegister2];
end
    
@(posedge Clk)
 if (RegWrite) 
    RF[WriteRegister] <= WriteData;
    
end

endmodule
what is wrong with the syntax here ? it has to do with the negedge and the assign... What I want to do here is assign ReadData 1 and 2 to a data on a negative clock edge
 
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