Reducing TTL to LV-TTL to conect Xilinx-CMOD circuit to parallel port

Discussion in 'General Electronics Chat' started by p4r4v4c4, Mar 12, 2010.

  1. p4r4v4c4

    Thread Starter New Member

    Mar 12, 2010
    I'm conecting a CMOD board from Xilinx (it has a Xilinx Coolrunner 2 CPLD) to the parallel port of my PC in order to read/write from/in it. The problem I have is that the logic levels from de port are TTL ('0'=0V and '1' or 'HZ'=5V) while my CMOD reads/writes voltages defined as LV-TTL, that is: '0'=0V and '1'=3,3V.
    Power supply Vcc of the CMOD board is 3,3 from a source generator. In my ignorance, i connected directly the port pins, to the CMOD pins, and when the port pins were at 'HZ' i observed that de source generator went from giving 3,3 volts to almost 4V! I suppose that happend because de current limit was exceeded. It's oviously not good...
    I guess i have to put some kind of regulator between each pin of de parallel port and the pins of the CMOD in order to reduce the voltage supplied by the port. Or should i put some resistances?
    I would kindly appreciate any suggestions and solutions as to how resolve this problem, specially since i have very little experience with this kind of circuit problems.
  2. t06afre

    AAC Fanatic!

    May 11, 2009
    Try using a 5 volt tolerant buffer. You have 3 types in the 7400 series that can do that.
    75LCX - CMOS with 3V supply and 5V tolerant inputs
    74LVC - Low voltage - 1.65 to 3.3V and 5V tolerant inputs, tpd<5.5nS@3.3V, tpd<
    74LVX - Low voltage - 3.3V with 5V tolerant inputs