Thank you, GeoRacer.Sorry for the late reply.
Clearly we are looking at two different functions. The solution function does not include the minterms 10 and 11, so it's a different problem.
Many thanks.I 'd also like to note that, in order to get NAND circuit, we use the F minterm expression. After you write F=C'D'+B (a Sum of Products) form, you double negate the expression and have a NAND circuit:
=((C' NAND) D') NAND B')
which is a NAND circuit.
If you want a NOR circuit, you have to work with the F' (maxterm) representation:
Now you double negate this form and get what you wish:
=(B' NOR D') NOR (B' NOR C')
which is a NOR circuit.
Actual after our last correspondence I read some of the pages from Mano's book (sorry to say that book sucks and is not for beginners ). The book says to implement a function using NAND logic you need to express the F in SoP form and it says a term with single literal requires an inverter in the first level; however if it's already complemented then it can be input directly into second level. Don't you find attached solution in my last post correct?You did the same steps, but you put the variable groups directly to the NAND circuit, essentially skipping over the double negation part. Had you tried to write the circuit expression only with NAND Boolean operations, you would have actively double-negate the F expression.
I haven't read about that rectangle rule. I have been through AAC e-book and I didn't come across such a rule there too. Please have a look on the attachment to see what I'm trying to say. Please help me with it because it's confusing me. Thank you.BUT! We do have a serious problem with K-map minimizations! Variable groups can only be rectangle and contain as many elements as powers of 2. This is very important. You cannot draw groups that do corners of contain 3 or 7 elements.
Thank you.Excellent! Now you nailed it!
One minute detail, just to be perfect: It's usually ok to draw the NOR gate as you did with the final one on the right, but to be clear, it's better in your final design to draw it as the ones on the left, with an OR gate and an inverter on top of it.
Now go to your other threads and correct any mistakes you have done in these K-maps.
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