Hello,

I've a +28V DC output from a SPMS Buck converter with a ringing phenomenon of 2V peak (or 4V pk-pk) as could see in the attached.


I've tried using many methods like:

1. RC snubber across switch node
2. RC snubber across V(gs) or even V(ds)

But all seems to be useless. Recently, I've read about EMI filtering blocks and I've bought one to use (Model: BNX002-01 http://search.murata.co.jp/Ceramy/image/img/PDF/ENG/L0117BNX00.pdf). See attached.

Unfortunately the results (as in the ringings) never change. Do anyone knows why?

The ringing period I've measured is about 80ns (hence about 12.6MHz).

What EMI block should I use? Anyone could help me?

 

You are getting ringing due to stray inductance and capacitance in the circuit. It's very difficult to build a breadboard SPMS without such ringing unless you are very careful about the layout. You need a ground plane for all common connections and need to keep all connections as short as possible between the switching transistor and all its related components, (input capacitor, drive circuit, free-wheeling diode, output inductor, etc.).

Trying to fix such ringing otherwise is difficult. You might try connecting a RC damping network (say 100pF with 47 ohms in series) directly from the switching transistor collector to ground (again, short leads).

 

you are getting ringing due to stray inductance and capacitance in the circuit. It's very difficult to build a breadboard spms without such ringing unless you are very careful about the layout. You need a ground plane for all common connections and need to keep all connections as short as possible between the switching transistor and all its related components, (input capacitor, drive circuit, free-wheeling diode, output inductor, etc.).

Trying to fix such ringing otherwise is difficult. You might try connecting a rc damping network (say 100pf with 47 ohms in series) directly from the switching transistor collector to ground (again, short leads).

hi crutschow,
do you have any idea of emi filter design?
Thanks.

 

hi crutschow,
do you have any idea of emi filter design?
Thanks.

Don't hijack this thread. If you have a specific question about EMI filter design start a new thread.

 

You are getting ringing due to stray inductance and capacitance in the circuit. It's very difficult to build a breadboard SPMS without such ringing unless you are very careful about the layout. You need a ground plane for all common connections and need to keep all connections as short as possible between the switching transistor and all its related components, (input capacitor, drive circuit, free-wheeling diode, output inductor, etc.).

Trying to fix such ringing otherwise is difficult. You might try connecting a RC damping network (say 100pF with 47 ohms in series) directly from the switching transistor collector to ground (again, short leads).

I've already separate the Analog GND with the power GND to reduce cross talk, and have packed all components as closely as possible. If assuming the buck system could no longer be modified. There should be something I could utilise? And I would like to know if that something is it a form of filter, ferrite bead, EMI filter block, customised 2nd-stage filter using 2*pi*f = 1/√(LC)?

I just need a direction so that I could start researching on that part! Please help!

 

Looking at the effective suppression frequency range (underlined in red), could anyone tell me why on the EMI filter block is not suppressing any of the transients at the very least?

Please note I've already seperate the control circuit GND with the power GND but to no avail.

 

Do you measure the noise with a normal load?

 

Do you measure the noise with a normal load?

not sure if an electronic load is a normal load for you?

Schematic of my buck is as attached. My e-load settings are set to draw constant current of about 3.5714A.

But the main point is not in my system, I would just need a device to damp out the high freq components (which is the 12.5 MHz noise) away from my constant +28V DC output. The device which I'm using (see pg 4 of http://search.alkon.net/cgi-bin/pdf.pl?pdfname=01105.pdf) has the capability of damping the noise of their circuit, but not for me!

Is it because their transient magnitude is of 0.5V only, while mine is a 2V high?

 

Did you try my recommendation of adding the damping circuit in post #2?

EMI is much easier to damp at it's source then to try to filter it out later.

 

Did you try my recommendation of adding the damping circuit in post #2?

EMI is much easier to damp at it's source then to try to filter it out later.

Hi Crutschow,

Im using a power MOSFET instead of IGBT, so if you meant collector, it should be referring to my drain terminal for my case.

Regarding your suggestion, I already have a 100uF bypass cap across +Vin and PSG (power GND). Wouldn't adding a 100pF in series with a resistor just add a minute difference from the already dominated 100uF? I read this from somewhere else and it does makes a little sense because I still can recall that capacitance adds up in parallel. Hence, adding a small cap will have neg. effect?

Or is it a 2nd stage filter you are intending?

 

The 100uF electrolytic cap doesn't work well as a capacitor in the MHz range.

You need to follow the current flow in you circuit when the switch is both on an off and minimize the length of that loop. Its the stray impedances in those two loops that contribute to the ringing. Thus you want to have 0.1uF caps connected at the input close to the switching transistor to shorten the length of the loop for the high frequency transients. The purpose of the RC network is to dampen the oscillations. Normally your connect it directly across the switching transistor (sorry I meant drain to source in my previous post).

Until you can identify and understand the current paths for the high frequency switch currents and figure out how to minimize there length, you are just shooting in the dark. Add on filters are a poor way to correct the EMI from a bad layout. Read this for a discussion on the critical current paths in the layout.

 

Thanks crutschow, the link is a good wealth of information.

I think I get what you mean. The input bypass cap (100uF) is too big to allow high freq response to dissipate the additional energy (or noise), effectively to the bypass cap. If I've a 80ns periodic high energy oscillations riding on a DC momentarily, is there a good way to calculate the req. C value to damp this particular freq noise?

Next, keeping leads short, would shorten the stray inductance from long leads which in the end may counter effect the series capacitance if it is not managed properly.

But I've another two quesitions:

1) Assuming the cause of the ringing originates from the nMOS during charging V(gs), as can be seen in the little ringing occuring in the middle (not end) when V(gs) charged up (see newly attached). Because of this, the +Vin or V(d) got affected, and also not sparing the switch node which then in turn carry forward the noise to my output.

How would a ceramic (say 0.1uF or better fine tuned values) effectively kill out the transient when the transient doesnt orginates from +Vin?

2) Also if a correct size ceramic cap could suppress the noise at +Vin, could we do it at Vout since the area of interest lies in there?

 

The 100uF electrolytic cap doesn't work well as a capacitor in the MHz range.

You need to follow the current flow in you circuit when the switch is both on an off and minimize the length of that loop. Its the stray impedances in those two loops that contribute to the ringing. Thus you want to have 0.1uF caps connected at the input close to the switching transistor to shorten the length of the loop for the high frequency transients. The purpose of the RC network is to dampen the oscillations. Normally your connect it directly across the switching transistor (sorry I meant drain to source in my previous post).

Until you can identify and understand the current paths for the high frequency switch currents and figure out how to minimize there length, you are just shooting in the dark. Add on filters are a poor way to correct the EMI from a bad layout. Read this for a discussion on the critical current paths in the layout.

Sorry crutschow,

According to the following forum discussion (http://www.electro-tech-online.com/...9740-dc-blocking-bypass-capacitor-values.html) which you happen to take part also in 2008, it says: "generically higher values are better for coupling as a higher capacitance will have a lower impedance at any given frequency". So in other words, higher capacitance generally provides lower impedance for any AC (including the noise I want to suppress?). Then why do you recommend me a 0.1MHz instead of retaining the 150uF? Because of the notorious inductance that inherit from Electrolytic cap??

 

Sorry crutschow,

According to the following forum discussion (http://www.electro-tech-online.com/...9740-dc-blocking-bypass-capacitor-values.html) which you happen to take part also in 2008, it says: "generically higher values are better for coupling as a higher capacitance will have a lower impedance at any given frequency". So in other words, higher capacitance generally provides lower impedance for any AC (including the noise I want to suppress?). Then why do you recommend me a 0.1MHz instead of retaining the 150uF? Because of the notorious inductance that inherit from Electrolytic cap??

You have it, grasshopper. Any small inductance in series with the capacitor will limit the capacitors minimum impedance at high frequencies. Even a short piece of wire can have enough inductance to be a factor.

And for the added capacitor at the MOSFET drain, you also want a small series resistor to dampen the oscillation energy, otherwise all you do is reduce the ringing frequency since the capacitor just looks like added capacitance to the LC tank.

 

With a board built of flying leads, radiated EM is impossible to kill because it radiates directly into the leads.

 

What is the Load on the supply?

 

Some portion of that ringing is due to your scope probe ground. You should always measure the output of a SMPS with a VERY short ground probe. The typical method is to remove the ground clip and wind some bus wire around the ground ring on the probe and leave a little bit sticking out to use as a ground lead. You want to measure that ringing directly across the output cap.

I would bet that almost half of your ringing is caused by the probe. The rest is mostly circuit layout. Only so much you cn do with a breadboard.

Have you thought about adding a second stage low pass filter on the output? Just a simple LC filter?

 

Some portion of that ringing is due to your scope probe ground. You should always measure the output of a SMPS with a VERY short ground probe.

The scope ground is not causing the ringing, it is simply an antenna which can pick it up.

I spent many years fighting this type of ringing in switchers, and you can usually kill or reduce it with a suitable R=C snubber applied across the offending component(s). The switch transistor usually needs a snubber, the switching transformer/inductor does as well.

The leads of the R=C snubber must be as short as possible. Wire length over an inch negates the snubber because of lead inductance.

Snubbers burn power as given by:

ps = c V (sq) x Freq

You can experiment with values and see what works best

 

What is the Load on the supply?

Hey Paul,

I am using electronics load which is drawing a steady 3.5714A.

 

Hi guys,

As advised, I've removed the 100uF Electrolytic cap and replaced it with a 10nF ceramic cap (that's because this is the biggest ceramic cap I've at the moment, my orders are coming in tomorrow).

Delighted, I've seen a tremedous attenuation of noise pk-pk signal to about a good 1V pk-pk! (see attached)

But the drawback seems to be that the nMOS gets heated up to about 200+ degrees celcius!(see attached) Could it be, because there is no R in series with my +Vin bypass cap and therefore the heat got dissipated in the mosfet through its intrinsic resistance instead?

Next observation made is there also seems a little trade off now at the noise occurring at the falling edge of V(gs).

My guess would be I need to add another capacitor across drain-source to suppress this turn-off transient?

I am so eager to get that overall suppression to a target of <0.8V (mainly 3% ripple).

EDIT: I know the loop from the input bypass cap, FET, schottky diode seems a little too big or long now, thats because because i need to solder the pin quick slot-in so that I could change the capacitance value conveniently. Once the value is finalised, I'll solder it firmly on the stripboard to reduce the loop area.