Race Hazards?

Thread Starter


Joined Sep 7, 2009
Hi all,

Wasn't sure exactly where to post this, but it seems more on level with the calibre of discussion here than elsewhere on the site.

Okay, so I'm building some simple adder/subtractor circuits in a lab, and one of the involved functions involved was the Sum(A,B,Cin) where Cin is the carry in and A and B are the two given input bits, and you get Sum=(A xor B) xor C = Ʃm(1,2,4,7). All would seem well in the world, except when I simulated this in PSpice, I got a hazard between minterms 1 and 2.

My guess is that this is being caused by a race hazard (moving from minterm 1 to minterm 2 is a diagonal on a KMap), but I'm unsure of how to 'fix' this problem, as this function's KMap gives very little to work with in terms of redundancies.

Any help would be greatly appreciated.


Joined Feb 12, 2009
I take it that once it has settled, you get the right result on your simulator?
But that due to differing gate delays you get race glitches?

This article:-
Shows a look-ahead-carry solution for increased speed for multiple bits.

In a real system, sufficient time would be allowed for the adder to settle before the result was stored (a fixed number of clock cycles).

Thread Starter


Joined Sep 7, 2009
Yeah, that's what I have as my current workaround. My prof. told me that there was some other implementation (no look ahead) that wouldn't yield this glitch. I have a feeling she's referring to another function or something, because I have no idea how else we could implement the function as-is and get the same result.

My other idea was to count in a different order... but again this is just a stupid kludgey mass of hardware.

At any rate, I appreciate your input and feedback.