Race Around Condition in SR FFs

Discussion in 'General Electronics Chat' started by ActivePower, Jan 2, 2014.

  1. ActivePower

    Thread Starter Active Member

    Mar 15, 2012
    I'm sure I am messing up terms here but I saw this question the other day which asked if a gated SR latch with NAND gates (schematic) would have a race-around condition and the answer was that it doesn't which got me confused.

    a) When we say that FF has an invalid state we do mean that the output is unpredictable and depends on the order in which signals reach the end. Is that condition not called a race hazard when two signals try to assert themselves at the same time?

    b) Is race-around another name for that or is it the case when the output cannot stay stable/keeps toggling due to improper clock pulse width selection?

    c) What the term for describing the situation in (a)?