My only question has to do with his small signal model representation.

With an NPN transitor like so, current should flow down into the emitter, out and to the left of the base and down through the collector right?

So in his small signal representation, should the current from the current source be flowing from emitter to collector or does he have it correct?

If so, why?

 

It's a PNP transistor by the way.

The key is to observe whether an instantaneously rising signal produces a instantaneously falling output signal - commensurate with the input-output phase inversion anticipated in a common emitter stage.

If vsig is increasing at some time instant, the base (vb) is being driven more positively, thereby tending to reduce vbe. Reducing vbe will reduce ic. Reducing ic will tend to reduce vo.

The small signal equivalent is consistent with the foregoing reasoning and it is therefore a true representation of the circuit.

 

It is an equivalent circuit, treating small-signal relationships. It does not represent bias currents or quiescent DC conditions in any way.

Note that the model output current will be zero for vsig=0, whereas the real circuit has 10mA quiescent current.