Looking at an XOR gate, you can make a NOT gate by tying one of the inputs to Vdd, but I can't see you can make an AND or OR gate.1) I hav seen some text's mention XOR gate as a universal gate...Is it true ?
If the hold-time is large and the contamination delay is small, then data in an edge-triggered pipeline (for example back-to-back registers) can become corrupted. This is the race condition, also known as a hold-time failure, and is only overcome through logic-system redesign and not by alteration of the clock-rate.2) Does an edge triggered circuit have race around problem......Isn't it applicable only to level triggered circuits..?
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