Questions about SMPS - buck converter. Pls help.

Discussion in 'General Electronics Chat' started by msoof, Jul 20, 2008.

  1. msoof

    Thread Starter New Member

    May 28, 2008
    hi all,

    i was trying to read up and find out more about how a SMPS (buck converter) works and came across this website. (

    Basically, this site has a series of lessons, as above, that explains the buck converter (including the importance of its frequency response).

    However, i have a few queries and i hope experts here in this forum can take some time to read up the site and try to answer my questions.

    My questions are as below:

    i have on some queries on topic - Buck Converter: AC model.

    on the says:"... OPEN LOOP AC RESPONSE
    Now that we've got our AC models, let's find the frequency (AC) response of the open-loop gain. Why? The gain and phase of the open loop provide critical insight how to compensate a control loop (Next topic). How do we open the loop? Pick a point to open the circuit such as where Vcontrol connects to ECMP of the PWM. Then connect an AC test source (VLOOP) to the point where the loop was opened (see circuit at top of page). Notice in the closed-loop version, node 10 would be connected to node 1.

    My questions:
    1. What are we doing when we feed AC test source (VLOOP) to the ECMP of the PWM? what does the AC test source waveform look like?

    2. The frequency of this AC test source is a representation of the SMPS switching frequency? if not, what can i relate this AC test source's frequency to? What happens if i varies the AC test source's frequency?

    3. Does the AC test source's frequency sortof signifies the rate of change of the error (Vref-Vo)?

    4. In the topic "buck converter - frequency compensation": the tuning mission states we have to (in the frequency domain) obtain a high bandwidth frequency (f_0dB). Why so?
    Also, at frequency = f_0dB, this is similar to the condition when Vcontrol is connected to ECMP of PWM?

    5. Also, the SMPS 'voltage mode control' block reads in the Vcontrol and adjusts the PWM accordingly. When the PWM is changed, does the switching frequency changes? or will it maintain the switching frequency BUT changes the duty cycle?

    6. If we isolate and just looked at the LC network, how should we select the L and C so that the cutoff frequency of the frequency response (of the LC network) is sufficient? How do we relate this cutoff frequency to our MOSFET switching frequency? Also, if our switching frequency does not change (and only the duty ratio changes), can we just set the LC cutoff to be much lower than the switching frequency?

    7. Lastly, Is this SMPS configuration (the voltage mode control theory, the error amplifier block etc) presented in this site a commonly-used configuration in most SMPS ICs?

    Looking forward to your reply.
    Thank you very very much.