Hi

(1) How much the ratio C2/C1 should be in order to start oscillations?
(2) If the output signal is taken from emitter through a suitable capacitor, how will be the feedback path to the base if the transistor?
(3) We all know that there is a stray capacitance came of external connections and the internal capacity of the transistor itself. If I use a 2n3904 transistor which has the following data:

My question is how much capacitance I should add to the series C1 and C2?
(4) Are there any effects from Cc cap on the oscillation frequency?
Thanks

 

What is the desired oscillation frequency?

 

I Know how to calculate the frequency,,,, suppose it is 100MHz

 

It's a fairly easy topology to get oscillating. I've got one going at the moment albeit at a much lower frequency [~800kHz]. I set a lower frequency simply because of the components and limited test options I have. I actually put Cc in series with the base rather than in series with the inductor. Your topology is more reminiscent of a Clapp oscillator - a modification of the Colpitts.

I believe one can get a pretty broad range of capacitance ratios C1/C2. It depends on simply getting enough closed loop gain to start and maintain oscillation. I would imagine a 5:1 ratio either way (C1/C2 or C2/C1) would work in principle. I note from some simulations that the capacitance ratio produces some significant differences in terms of the operating mode. Although seemingly biased in the linear region, once oscillations build up the transistor operates at or beyond cut-off : somewhere between a Class B and Class C it seems. In my working circuit with C1=C2 the base-emitter junction bias is an average of about -0.75V. In other words biased well beyond cutoff when oscillating. So whilst the output will be approaching sinusoidal, the collector and emitter current will be pulses at the oscillation frequency - definitely not sinusoidal.

In terms of undertaking a predictive / modelling analysis, this highly non-linear operating condition makes it difficult to know whether oscillations will start or not with any given set of component values. With the transistor biased beyond cut-off, the oscillator output impedance at the emitter is difficult to estimate other than by simulation or direct measurement. One needs to know this impedance to do an approximate open loop linear analysis to decide whether the gain and phase shift are consistent with oscillation conditions. In my case I used R1=R2=15k and RE=1k with a 5V supply. The Rout is about 700Ω when oscillating - as deduced by simulation at different capacitively coupled loads. Using this value in an open loop simulation gives a good agreement for the predicted operating frequency - per the Barkhausen criterion. Even though I have moved Cc into the base it still plays a role in the success or otherwise of operation - it is another impedance which effects the open loop gain.

FYI the values I have are

DC supply=5V, Transistor BC337, L=40uH, C1=C2=2.2nF, R1=R2=15kΩ, RE=1kΩ and Cc=100nF [in series with the base], fo=770kHz.

When I have some time I'll play around with some values to get a better feeling for the limiting conditions. Trying to gauge the effects of the BJT parasitic capacitances might not be possible for me in practice.

 

It's a fairly easy topology to get oscillating. I've got one going at the moment albeit at a much lower frequency [~800kHz]. I set a lower frequency simply because of the components and limited test options I have. I actually put Cc in series with the base rather than in series with the inductor. Your topology is more reminiscent of a Clapp oscillator - a modification of the Colpitts.

yes it is clapp not colpitts

I believe one can get a pretty broad range of capacitance ratios C1/C2. It depends on simply getting enough closed loop gain to start and maintain oscillation.

How do I know that getting enough closed loop gain?
What to watch? What to Calc? What to measure?

In my case I used R1=R2=15k and RE=1k with a 5V supply. The Rout is about 700Ω when oscillating - as deduced by simulation at different capacitively coupled loads.

how you measure the 700 Ω?

Here is my design

Firstly i designed an emitter follower of Q-point (IC= 1mA and VCE = 1,5 V)
then I calculate the tunning circuit:

when I stand in order to explain it to my colleagues, I expect to ask me
1 - Why did you choose this ratio for C2/C1 = 0.5?
2 - How will feedback path from emitter to base?
3 - How was stray capacitance value calculated using the 2n3904 transistor datasheet?
4 - How the capacity divider works? i.e how it matching the impedances between low emitter and high base?
5-What relationship of loaded Q to this ratio (C2/C1)?
So I need your help so I do not feel overwhelmed
thank you

 

The minimum value one would choose for C2 (say) would be that capacitance (acting alone) which would give the required resonant frequency with the given inductance. This would require an infinite value for C1 (ridiculous) but it sets a benchmark for C2. One then would presumably decide on a higher value of C2 and a commensurate C1 to give the required operating frequency. The question then remains - will the circuit oscillate? Would a 10:1 ratio for C1:C2 work?

A means to resolve the question is to try a linearized open loop model to see if the open loop gain / phase plot gives the 0° phase shift and minimum unity gain condition necessary for sustained oscillation. Some people would argue that the high non-linearity and large signal mode of the BJT would preclude such an analysis - but it seems to work in practice [at least for low frequency analysis where parasitics aren't significant]

I've attached a linearized model of your schematic based on a few assumptions.
Rout for the emitter follower is say 500Ω.
The emitter follower has a gain of 0.9
The resonant circuit load is of the order of 10kΩ.

If I alter C1 & C2 to note when the linearized open loop gain is not sufficient to guarantee oscillation, I find that the limiting C1:C2 ratio is about 5:1. If I use C1=40pF and C2=8pF to give the series equivalent of C1=20pF and C1=10pF then the gain is just above unity at the 0 degree phase shift condition. If I apply these values in the actual loaded oscillator simulation then oscillation just occurs with the 2N3904 but fails with the BF199 - presumably the lower beta value compromises the BF199 in this instance [see last paragraph re BJT choice]. So a C1:C2 ratio of 5:1 gives oscillation in some circumstances - indicating a limiting condition which one would not exceed in practice.

You'll note from the gain / phase plots your values show a zero phase / unity gain condition at around 190MHz. Your simulated frequency is around 150MHz which clearly suggests that the BJT parasitic capacitances are playing a significant role in determining the actual frequency. This isn't surprising given your relatively low capacitance values which are perhaps only an order of magnitude (or less) higher than the parasitic values.

As a cross check I've simulated your schematic and with the BJT a 2N3904 I observe an unloaded frequency of about 140MHz and a loaded [500 ohm + 1nF] frequency of about 160MHz. When I swap to a BF199 [with a higher transition frequency than the 2N3904], I obtain a loaded frequency of about 180MHz indicating the comparative effect of BJT parasitic capacitance.

 

Just a comment on topology: Connect the inductor to the base, move the R2:R4 bias divider to the other end of the inductor, and bypass the divider to GND with a cap.
This increases the Q slightly. With the original topology, the Thevenin resistance of the divider is in parallel with the inductor.
I was able to get simulated oscillation with C1=6.8pF, C2=100pF. I'm not saying I recommend this for hardware. I'm just saying.