question related to D F/F.

Thread Starter

Anirudhgoud

Joined Feb 8, 2012
4
In the D F/F,if the input transition changes form 1->0 for the D input and the clock enable is given or change from 0->1 what would be the output??
And which of the two values has to be considered for input in either cases for D input and the clock enable?? :confused:


 

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crutschow

Joined Mar 14, 2008
25,389
D determines that state of the output after the clock is enabled. Normally D is considered the controlling input and the clock is considered the enable input. Typically you change the state of D with the clock is 0 and then the FF changes to the state as determined by the D input when the clock goes high.

If the D is 1 when the clock is 1 then Q will be 1.

Understand that this is not the usual type of FF that you buy in a chip. Those FFs are master-slave type which only change state on the clock transition and are insensitive to the static state of the clock, unlike the FF you show.
 

Thread Starter

Anirudhgoud

Joined Feb 8, 2012
4
Thank you very much for the answer i would appreciate if you could tell me which input should be considered if there is a transition from 0->1 and 1->0 in specific..
 

SgtWookie

Joined Jul 17, 2007
22,220
For this circuit, if the clock is high, the Q out will be the same as what's on the D in.

With a real D-type FF, the D input is copied to the Q out only when the clock transitions from low to high; it is triggered by the rising edge. The rest of the time, the D input is ignored.
 

Thread Starter

Anirudhgoud

Joined Feb 8, 2012
4
How can that be a gated RS,here there aren't two different inputs,one input is inverted and given to the second and that's the D-F/F??
 

joeyd999

Joined Jun 6, 2011
4,429
How can that be a gated RS,here there aren't two different inputs,one input is inverted and given to the second and that's the D-F/F??
The two AND gates are the 'gated' portion of the RS. I see the inverter as simply a matter of convenience for this particular circuit. Remove it, and you have a true gated RS.

BTW, Wikipedia calls this configuration a 'Gated D Latch', 'one-input synchronous SR latch', 'transparent latch', 'data latch', or 'gated latch'. Whatever the name, it is not a proper D flip flop.
 
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