Good morning everyone,

I am a bit confused regarding the simple circuit I found in the book, maybe because I lost some important information long the way because I'm not a native speaker..
However, when the imput is low at the base of the first npn, the voltage across C1 is around 4.4 V, because on the left is at 5, on the right is about 0.6-0.7 due to the Q2 npn and that is obviously fine.

My question is why does the voltage at the second npn (Q2) becomes - 4.4V when the imput goes high at 5V?
Why not - 0.6V as the voltage across C1?

I even tried to simulate it a bit slower on ltSPICE but the result is quite similar.

Thank you,

 

hi AM,
Welcome to AAC.
As you say when Q1 Base is at 0V , Q1 is not conducting, so Q1 Collector is at +5v.
So there a voltage of 5V -0.7V across the capacitor.
When Q1 starts to conduct, the positive charged end of the capacitor is grounded to 0v, so the other end of the capacitor is at -4.3v with respect to 0V.
This turns Off Q2, but remember the Q1 Base to Emitter internal diode is reverse biassed, so the -4.4v will hold Off Q2 until the capacitor discharges via R2
Ref your LTS diagram.
E

 

1 milli (m) = 1,000,000.00 nano (n)
the capacitor is 10nF
ltspice calls square wave a pulse to use it find " independent voltage source" then select pulse or
PULSE(Voff Von Tdelay Trise Tfall Ton Tperiod Ncycles)
it can do much more it is like a function generator. search for: setting the ltspice independent voltage source.