Hi,

I'm using a binary ripple counter and have the outputs of the 1st bit and 7th bit running into an AND gate. Because of the propogation delay as the signal goes through each flip flop, there is a few hundred nanoseconds between when the 1st bit and 7th bit reach the gate causing the first period of the higher frequency signal to be short and for there to be a tiny, unwanted spike at the very end. I was wondering if anyone had any advice on how to get the two signals to line up.

Thanks

 

two methods come to mind: Use a Johnson counter in which all stages are clocked simultaneously (preferred) or add extra delay to the signal from the 1st output (Klugy but works).

The delay can be made by just adding inverters in series with the signal or, if you are just making one, put a resistor in series with the output of the first pulse -say 10k, and then whatever capacitor happens to make the glitch on the output of the gate go away from where the resistor connects to the gate's input to ground.

I say go with the Johnson counter if you can. Have a look at the 74HC4017 data sheet for more.

 

Well, I'm using the counter as a frequency divider so I don't think the Johnson counter will work right. And I have a few unused and gates that I was going to run the signal through to slow it down, like what you suggested, the only problem there is that the delay on those is like 20ns so I would have to use like ten of them.

 

i'm curious as to which counter you are using.

 

I'm using a 4060 counter with a 57kHz clock. I would just put a resistor in series and capacitor in parallel with the AND gate input that I want to delay, which would work, but the threshold voltages on the gates are not well defined so I wouldn't be able to control it.

I had a similar problem elsewhere in the circuit where I had two of the outputs going into an or gate, which caused an unwanted very short break in the high signal, but I was able to correct that with a simple RC low pass filter. I was just reading about all pass filters and that sounds like what I want, but maybe a little more complicated than I was expecting.

 

Actually, I know they do make synchronous binary counters that would solve my problem, but they seem way more expensive than want and don't have the bit count that I need in a single chip.

 

ah. you'll have to forgive my limited knowledge. but i'm curious as i've worked with the 4040 a number of times. i've often been able to solve issues by using schmitt triggers.
what is the divide-by function you're going for?

 

What I'm trying to do is create a 600us burst of 57kHz followed by a 2ms rest. The AND gate is whats controlling the 57kHz burst and I want the inputs to match up so that they don't cause a higher frequency at the beginning and end of the signal