Hello i am new on fpga and verilog.in this code i have taken input from keypad and want to make a calculator and display on lcd.help me in code please how to make alu of calculator and modification in this code regarding input and how to display on 8 bit lcd please help.
Rich (BB code):
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:53:29 10/15/2011
// Design Name:
// Module Name: kepad
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module kepad(
input [3:0] in1,
output reg [3:0] out1,
output reg [3:0] sevenseg,
input clk
);
reg [3:0] num1=0;
reg [3:0] num2=0;
reg [3:0] opr=0;
reg [1:0] count=0;
//in1 = in1;
//out1=out1
// sevenseg=0;
always@(posedge clk)
begin
out1=1;
if(in1==8)
sevenseg=7;
if(in1==4)
sevenseg=4;
if(in1==2)
sevenseg=1;
if(in1==1)
sevenseg=10; //10=reset
out1=2;
if(in1==8)
sevenseg=8;
if(in1==4)
sevenseg=5;
if(in1==2)
sevenseg=2;
if(in1==1)
sevenseg=0;
out1=4;
if(in1==8)
sevenseg=9;
if(in1==4)
sevenseg=6;
if(in1==2)
sevenseg=3; //missed '11'
if(in1==1)
sevenseg=12; //12='='
out1=8;
if(in1==8)
sevenseg=13; //13=/
if(in1==4)
sevenseg=14; //14=*
if(in1==2)
sevenseg=15; //15=-
if(in1==1)
sevenseg=16; //16=+
end
always@(sevenseg)
begin
count=count+1;
end
always@ (sevenseg or count)
case(count)
2'd0: opr=12;
2'd1: num1=sevenseg;
2'd2: opr=sevenseg;
2'd3: num2=sevenseg;
default: opr=0;
endcase
//if(count==3)
//
endmodule