hi,
I build my common-drain amplifier by referring to common-source amplifier which using a voltage divider to bias the E-mosfet. The CD circuit is as below.
R1=100k R2=19K RS=100 and RL=10k Vdd=+10V
When i input in 40mVp-p sine wave, i cant get any result at the output part. Vgs=0 which means the 2n7000 is not biasing. Anyone can help me on this? Isnt it the voltage divider should bias the mosfet ?thanks.
I build my common-drain amplifier by referring to common-source amplifier which using a voltage divider to bias the E-mosfet. The CD circuit is as below.
R1=100k R2=19K RS=100 and RL=10k Vdd=+10V
When i input in 40mVp-p sine wave, i cant get any result at the output part. Vgs=0 which means the 2n7000 is not biasing. Anyone can help me on this? Isnt it the voltage divider should bias the mosfet ?thanks.