PSpice Model Editor Not Giving .dll and .lib Files for VerilogA Module

Thread Starter

the_keola

Joined Mar 23, 2021
2
Hello,

I am trying to learn how to import VerilogA Modules into PSpice using the Model Editor. For now I am starting with a simple VerilogA model of a capacitor so I can learn how to use the Model Editor and then eventually get to more complex VerilogA implementations. I have been unsuccessful in using the Model Editor DMI Template Code Generator and I'm unsure what the problem was. Here is the simple Verilog module:

'include "disciplines.vams"
module cap(p,n) ;
parameter real capacitance = 1n ;
electrical p, n ;
analog
I(p,n) <+ capacitance * ddt(V(p,n)) ;
endmodule


I saved this using notepad as "cap.va" and then used the DMI Template Generator. Here are the steps I did for that:

1. Part Name - "cap"
2. Part Type - VerilogA-ADMS
3. Verilog-A File --> Selected "cap.va" file
4. XML Folder --> Left as is
5. Output --> Selected the DLL Location

When I hit the OK button the log file pops up but it ends with a "child process exited abnormally" message and there are no .dll or .lib files in the DLL Location. Here is the resulting "cap.log" file:

Reading json
reading Model Name and Type...
Json read..Logging Model Creation...
reading global and instance params for digital and analog..
Copying common files ..
Replacing the Model Name in C:\Cadence\SPB_17.4\tools\pspice\tclscripts\pspModelCreate\VerilogATemplate\xmls\pspiceVersion.xml
Verilog-A Path : D:/cap.va
Name of Verilog-A file : cap.va
Verilog-A Location : D:/
XMLs Location : C:\Cadence\SPB_17.4\tools\pspice\tclscripts\pspModelCreate\VerilogA-ADMS\xmls
Generating Files
C:\Cadence\SPB_17.4\tools\pspice\tclscripts\pspModelCreate\VerilogATemplate/admsXml.exe -I D:/ D:/cap.va -e D:/ORCAD_PARTS/cap/code/pspiceVersion.xml -e C:\Cadence\SPB_17.4\tools\pspice\tclscripts\pspModelCreate\VerilogA-ADMS\xmls/pspice.lib.xml
[info...] admsXml-2.3.0 (1186M) Aug 4 2010 10:25:25
child process exited abnormally


Did I end up doing something wrong or is there something wrong with the VerilogA File?
 
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