can some one help me making the ic package from it functional block diagram to make it in working state which is ready for simulation , i dont know how to make a custom IC with the same functionality in the software . Please help me making the IC. the data sheet is attached.

 

[eta]
This topic apparently is a continuation of this thread:
http://forum.allaboutcircuits.com/showthread.php?t=62405
I see no reason why they can't be merged.
[/eta]

Do you have the IR2104 in your library?
http://www.irf.com/product-info/datasheets/data/ir2104.pdf
It's fairly similar, but has less source/sink capability, a shorter dead time, and a SD\ input.

Just connect SD\ to GND (COM must also go to GND) and you should be able to use it as a substitute for simulation's sake. If it has enough dead-time with this driver, then it certainly will have enough with the IR2111.

I do not have Multisim, so I cannot help you.

 

will it work same as IR2111 , i mean the output will be the same in circuit.

 

It won't be exactly the same. Read the datasheet.

The IR2111 has a higher current source and sink capacity, and a longer dead-time.

If your circuit simulates with the IR2104, then it would simulate with the IR2111, if there were a proper model of it.

You can experiment with the IR2104 model, and make changes so that it has the same performance as the IR2111. You will need to do a lot of research on how to create/change SPICE models.

 

Are you trying to simulate the circuit because the PCB that you made in this thread:
http://forum.allaboutcircuits.com/showthread.php?t=46846&page=6
... from the files in reply #59? you posted a year ago?

I did not look at those before, as I had an older version of Eagle installed. You have many, many errors in the schematic "Layout exercise (1).sch". You obviously did not use the Erc function, or if you did, you didn't bother to clean up the error messages.

See the attached list image.

One of the most important warnings is that there is only one pin on net +24V - that means you labeled it, but it doesn't connect to anything else.

 

i am using the following design that is in eagle , dnt forget to add rats net

 

You are using 1N400x series diodes for the boost supply. That won't work very well.

Use something like 1N4148, 1N914, or more preferably something Schottky, like 1N5819 or a BATnn diode.

I don't know why, but you have chosen to place your MOSFETs far, far apart - in the case of Q3 & Q4, on opposite sides of the board. The gate trace for Q3 is reasonably short, but the drain and source traces make a Grand Tour of the Board. You may not realize this, but there will be a fair amount of inductance in those long, relatively thin traces; and that inductance spells trouble. You should have started off by placing the pairs of MOSFETs very close together, and then the IR2111's right next to them. As it is, you have traces making long, circuitous loops for no really good reason.

Use a trace calculator to get an idea what trace inductance will be.

Read through this page:
http://www.analog.com/library/analogdialogue/archives/39-09/layout.html

Use this page for calculating your required trace widths:
http://circuitcalculator.com/wordpress/2006/01/31/pcb-trace-width-calculator/

 

Here, I've updated mainly the board, but I also changed a couple of the diodes from 1N4004 to 1N5819's. I don't know what kind of current you are planning on, but the 1A 1N4004 diodes in the +24v line will act as fuses if you exceed their rating for very long.

I left the board the original size; I didn't know if you needed it that size for a particular reason. You can see it's more compact now.

I also gave several important nodes names, so it was easy to see how long they are. For example, in the board command line, type:
SHOW A
SHOW B
SHOW 12V
SHOW 24V
SHOW 24VEXT
SHOW GND
etc.
Try looking at nodes in your previous board version as well; but your signal names will be different.

I don't know what kind of heat sinks you are planning on using. However, the important thing was to start off getting all the main power items close together, give them big fat traces, and minimize the length of the gate traces, too.