A little on my background and reason for this question.
I am an EEE engineer (wasted my college years as I didn't have any interest in electronics at that time ).
Then I got my first software engineering job, designing software for creating embedded hardware design ( which made me started hating software and loving hardware side of things ). And now I am slowly moving towards system design engineering.

I am working on integration of an arm based SOC with FPGA as of now. That's when I realized I need to get hold of my basics to be a better design engineer. I particularly got struck on memory address mappings done for processor to memory. I tried grasping it through material available on internet and got a basic understanding. But I seriously doubt that my perception of it is the correct one and hence stated some part of my understandings in the simplest possible manner I could (and have reserved the complexities for later posts ). Here I have presented the various processor architectures and my doubts related to each one of them. If someone could read through it and guide me through my mistakes, It would be a great help.

Here's the simplistic description which I have in my mind about the various architectures and their pros and cons:
For each of the architecture I have assumed that an address bus is 1 bit wide and data bus is 8 bit wide:

1) Harvard Architecture:

Processor has two address buses (each 1 bit):
Instruction address bus: (IAB)
Data address bus: (DAB)

Processor has two data buses (8 bit each):
Instruction data bus: (IDB)
Data data bus: (DDB)

Processor has two separate memories(each is 16 bit -> 2x8):
instruction memory: (IM)
data memory: (DM)

When the processor needs to fetch an instruction, it will generate an address 0 or 1 which will go to IM through IAB and fetch the 8 bit instruction at that location(based on whether IAB has value 0 or 1) through IDB.
Similarly, If the processor needs to fetch some data or write to some location, it will go to DM through DAB and fetch the data at that location through DDB.

Salient Features of this architecture:
1) Possible to fetch instruction and data at the same time.
2) Effectively we'll have 32 bit memory (16 for IM and 16 for DM). Though I am not sure if its a positive feature or a negative one.
3) Processor will occupy more area. Is it true?
4) Instruction set would be complex. Again, is it true?

2) Modified harvard architecture:

Processor has two address buses (each 1 bit):
Instruction address bus: (IAB)
Data address bus: (DAB)

Processor has two data buses (8 bit each):
Instruction data bus: (IDB)
Data data bus: (DDB)

Processor has a single memory 'M'.
At location 0 resides the instruction and at location 1 resides the data. IAB will be mapped only to location 0 of memory and DAB will be mapped only to location 1 of memory.

When the proccesor want to fetch the instruction, it will ask for location 0 through IAB and fetch the instruction through IDB. Similar process would be done to fetch data at location 1, though this time through DAB and DDB.

Salient features:
2) Still we can fetch data and instruction at the same time.
1) Need only one memory space.
2) Effective memory is 16 bit. That is bad, right?
3) One doubt is what happens if processor tries to access location 1 through IAB or location 0 through DAB. How is this situation taken care of?

3) Von Neumann architecture:

Processor has one address buses (1 bit):
Common address bus: (CAB)

Processor has one data buses (8 bit):
Common data bus: (CDB)

Processor has a single memory 'M'.
At location 0 resides the instruction and at location 1 resides the data. CAB will be mapped to both location 0 and 1.

When the processor wants to fetch an instruction, it will go to location 0 through CAD and fetch the data there through CDB. Similarly for data, it will go to location in a similar manner.

One of the basic question I have with respect to Von Neumann architecture is that when we are trying to fetch an instruction or data, the processor will just give an address location (say suppose 0) to the CAB. How would it know if its for data or instruction? Because what I believe is that in harvard architecture, the fact that it went through IAB meant it was an instruction and DAB meant it was data. But having a common bus in von neumenn would not provide any such differentiation.

Thanks for the help in Advance

 

In Von Neumann the first thing fetched from the common memory is the opcode (instruction type ADD, GOTO etc). This is decoded by the instruction execution unit which then 'knows' how many more bytes/words to fetch to complete the instruction. After all of the bytes/words are fetched the instruction is executed by the CPU. After the correct number of bytes/words have been fetched for the entire instruction the address counter (Program Counter) points naturally to the first byte/word of the next instruction (another opcode).

The execution unit can be implemented as a state machine or in microcode. A micro-programmed CPU takes the opcode as a pointer to the starting point of a sequence of micro instructions that work the CPU hardware (busses, registers etc) to fetch any remaining bytes/words to temp registers (advancing the PC each time) and executing the instruction by shuttling data around to where it needs to be. Each CPU instruction can take many micro-instructions to complete which is why you see various instructions take different numbers of CPU clock cycles to execute.

Von Neumann/Harvard each have advantages and disadvantages. Von Neumann allows all memory to have the same word size at the expense of needing multibyte (and multi cycle) instructions. Very complex instructions can be implemented. Harvard allows the program memory to have a different word size than the data memory. This allows 8 bit data while having an instruction size large enough to specify the entire CPU instruction in one fetch from memory, speeding execution at the cost of fewer, less powerful instructions and usually, some special requirements to access program memory for tables, etc.