This should be a purely simulation artifact since the D input is ignored unless the clock transitions. I checked the datasheet for the 74HC7474 and it doesn't have any timing specification at all for the /R relative to the D inputs, so they are claiming that no race conditions (at least not critical races) exist between those two signals.The circuit logic would seem to be ok. But I have also seem some odd results at times under certain simulation conditions. There appears to be some odd race condition that sometimes occurs when the D input and the /Reset go high at the same time. Perhaps a small delay is needed between the time the D input goes high and the /Reset goes high.
by Aaron Carman
by Jake Hertz
by Aaron Carman
by Jake Hertz