problem on memory write policy

Thread Starter

braddy

Joined Dec 29, 2004
83
Hi,
I am really struggling with this problem. I have no idea how to start it.
It is about computer architecture.

here is the problem:

One difference between a write-through cache and a write-back cache can be in the time it takes to write. During the first cycle, we detect whether a hit will occur, and during the second (assuming a hit) we actually write the data. Let’s assume that 50% of the blocks are dirty for a write-back cache. For this question, assume that the write buffer for the write through will never stall the CPU (no penalty).

Assume a cache read hit takes 1 clock cycle, the cache miss penalty is 50 clock cycles, and a block write from the cache to main memory takes 50 clock cycles.

Finally, assume the instruction cache miss rate is 0.5% and the data cache miss rate is 1%. Assuming that on average 26% and 9% of instructions in the workload are loads and stores, respectively, estimate the performance of a write-through cache with a two-cycle write versus a write-back cache with a two-cycle write.


One question that come to my mind is how can I find the CPI from these info?

If somebody understand it, please i would appreciate any suggestions.
Thank you
 
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